Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2008-06-17
2008-06-17
Le, Thao P. (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257S316000
Reexamination Certificate
active
07387932
ABSTRACT:
A method for manufacturing a multiple-gate memory cell which comprises a semiconductor body and a plurality of gates arranged in series and the semiconductor body includes first forming a plurality of gates spaced apart by about a gate width, forming an isolation layer on the sidewalls, and filling between the first plurality of gates to form a second plurality of gates. A charge storage structure is formed on the semiconductor body beneath each of all or some of the gates in the plurality of gates. Circuitry is formed to conduct source and drain bias voltages to the semiconductor body near a first gate and a last gate in the series, and circuitry to conduct gate bias voltages to the plurality of gates is included. The multiple-gate memory cell includes a continuous, multiple-gate channel region beneath the plurality of gates in the series, with charge storage locations between some or all of the gates.
REFERENCES:
patent: 4959812 (1990-09-01), Momodomi et al.
patent: 5270969 (1993-12-01), Iwahashi
patent: 5278439 (1994-01-01), Ma et al.
patent: 5408115 (1995-04-01), Chang
patent: 5412603 (1995-05-01), Schreck et al.
patent: 5448517 (1995-09-01), Iwahashi
patent: 5515324 (1996-05-01), Tanaka
patent: 5753950 (1998-05-01), Kojima
patent: 5768192 (1998-06-01), Eitan
patent: RE35838 (1998-07-01), Momodomi et al.
patent: 5877054 (1999-03-01), Yamauchi
patent: 5895949 (1999-04-01), Endoh
patent: 6011725 (2000-01-01), Eitan
patent: 6096603 (2000-08-01), Chang et al.
patent: 6151248 (2000-11-01), Harari et al.
patent: 6194272 (2001-02-01), Sung
patent: 6356478 (2002-03-01), McCollum
patent: 6522585 (2003-02-01), Pasternak
patent: 6552386 (2003-04-01), Wu
patent: 6614070 (2003-09-01), Hirose et al.
patent: 6645813 (2003-11-01), Hsieh
patent: 6657894 (2003-12-01), Yeh et al.
patent: 6670240 (2003-12-01), Ogura et al.
patent: 6670671 (2003-12-01), Sasago et al.
patent: 6690601 (2004-02-01), Yeh et al.
patent: 6714457 (2004-03-01), Hsu et al.
patent: 6798012 (2004-09-01), Ma et al.
patent: 6856551 (2005-02-01), Mokhlesi
patent: 6885044 (2005-04-01), Ding
patent: 6933555 (2005-08-01), Hsieh
patent: 6995424 (2006-02-01), Lee
patent: 7018895 (2006-03-01), Ding
patent: 7026682 (2006-04-01), Chung
patent: 7071061 (2006-07-01), Pittikoun
patent: 7078762 (2006-07-01), Ishii et al.
patent: 7106625 (2006-09-01), Yeh
patent: 7120059 (2006-10-01), Yeh
patent: 7166513 (2007-01-01), Hsu et al.
patent: 2001/0012663 (2001-08-01), Magri' et al.
patent: 2003/0025147 (2003-02-01), Nomoto et al.
patent: 2003/0067032 (2003-04-01), Caprara et al.
patent: 2004/0084714 (2004-05-01), Ishii et al.
patent: 2004/0145024 (2004-07-01), Chen et al.
patent: 2005/0001258 (2005-01-01), Forbes
patent: 2005/0062091 (2005-03-01), Ding
patent: 2005/0218522 (2005-10-01), Nomoto et al.
patent: 2005/0255652 (2005-11-01), Nomoto et al.
patent: 2006/0044872 (2006-03-01), Nazarian
patent: 2006/0197145 (2006-09-01), Pittikoun et al.
patent: 2006/0202256 (2006-09-01), Harari
patent: 2006/0234446 (2006-10-01), Wei et al.
patent: 2006/0275986 (2006-12-01), Kobayashi et al.
patent: 2007/0032018 (2007-02-01), Tuntasood et al.
U.S. Appl. No. 10/855,286, filed May 26, 2004, entitled “NAND-Type Non-Volatile Memory Cell and Method for Operating Same,” 15 pages.
U.S. Appl. No. 11/085,458, filed Mar. 21, 2005, entitled “Charge Trapping Non-Volatile Memory and Method for Gate-By-Gate Erase for Same,” 73 pages.
U.S. Appl. No. 11/085,325, filed Mar. 21, 2005, entitled “Memory Array Including Multiple-Gate Charge Trapping Non-Volatile Cells,” 74 pages.
U.S. Appl. No. 11/085,300, filed Mar. 21, 2005, entitled “Charge Trapping Non-Volatile Memory and Method for Operating Same,” 73 pages.
U.S. Appl. No. 60/585,657, filed Jul. 6, 2004, entitled “Programmable and Erasable Charge Trapping Non-Volatile Memory Cell and Method of Operating Same,” 32 pages.
U.S. Appl. No. 60/585,658, filed Jul. 6, 2004, entitled “Charge Trapping Non-Volatile Memory Cell and Method of Operating Same,” 26 pages.
U.S. Appl. No. 11/118,839, filed Apr. 29, 2005, entitled “Inversion Bit Line, Charge Trapping Non-Volatile Memory and Method of Operating Same,” 34 pages.
U.S. Appl. No. 11/085,326, Mar. 21, 2005, entitled“ Charge Trapping Non-Volatile Memory With Two Trapping Locations Per Gate, and Method for Operating Same,” 73 pages.
Chang, Kuo-Tung, et al., “A New SONOS Memory Using Source-Side Injection for Programming,” IEEE Electron Device Letters, vol. 19, No. 7, Jul. 1998, 253-255.
Eitan, Boaz, et al., “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Letters, vol. 21, No. 11, Nov. 2000, 543-545.
Fujiwara, I., et al., “0.13 μm MONOS single transistor memory cell with separated source lines,” IEDM 1998, 995-998.
Kobayashi, T., et al., “A Giga-Scale Assist-Gate (AG)-AND-Type Flash Memory Cell with 20-MB/s Programming Throughput for Content-Downloading Applications,” IEDM 2001, 2.2.1-2.2.4.
Naruke, K., et al., “Nonvolatile Semiconductor Memories: Technologies, design and application,” C. Hu. Ed., New York, IEEE Press, 1991, Ch. 5, pp. 183-186.
Sasago, Y, et al., “90-nm-node multi-level AG-AND type flash memory with cell size of true 2 F2/bit and programming throughput of 10 MB/s,” IEEE, 2003, 4 pages.
Lahiri, S. K., “MNOS/Floating-Gate Charge Coupled Devices for High Density EEPROMS: A New Concept”, Physics of Semiconductor Devices, Dec. 1997, pp. 951-956, vol. 3316, No. 2.
Lee, Jae-Duk, et al., “Effects of Floating-Gate Interference on NAND Flash Memory Cell Operation,” IEEE Electron Device Letters, vol. 23, No. 5, May 2002, 264-266.
Shin, Yoocheol, et al., “High Reliable SONOS-type NAND Flash Memory Cell with AI203 for Top Oxide,” Non-Volatile Semiconductor Memory Workshop, 2003, 2 pages.
Haynes Beffel & Wolfeld LLP
Le Thao P.
Macronix International Co. Ltd.
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