Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2008-07-08
2008-07-08
Lebentritt, Michael S. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S258000, C438S761000, C438S763000, C438S261000, C438S149000, C438S366000, C257S499000, C257SE21645, C257SE21680
Reexamination Certificate
active
07396723
ABSTRACT:
A method of manufacturing an EEPROM device can reduce the cell area. The method of manufacturing an Electrically Erasable Programmable Read-Only Memory (EEPROM) includes forming a mask pattern over a semiconductor substrate; forming a gate oxide layer over a top of the semiconductor substrate exposed through the mask pattern; forming access gates which are self-aligned with both side walls of the mask pattern, over a top of the gate oxide layer; removing the mask pattern; forming first dielectric spacers to be attached to side walls of the access gates; forming an insulating layer adapted to cover the access gates and the first dielectric spacers; and forming two cell gates, which are self-aligned with opposite side walls of the two access gates, respectively, each first dielectric spacer being interposed between a corresponding cell gate and a corresponding access gate, the cell gates separately arranged over a top of the insulating layer.
REFERENCES:
patent: 6326316 (2001-12-01), Kiyotoshi et al.
patent: 6359305 (2002-03-01), Chiu
patent: 7064378 (2006-06-01), Jeon et al.
Ahmadi Mohsen
Dongbu Hi-Tek Co., Ltd.
Lebentritt Michael S.
Sherr & Nourse, PLLC
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