Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2008-05-13
2008-05-13
Trimmings, John P (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S003000, C714S006130, C714S025000, C714S048000, C714S723000, C714S726000, C714S727000, C714S729000, C714S741000, C714S746000
Reexamination Certificate
active
07373567
ABSTRACT:
A system and method of providing error detection and correction capability in an IC using redundant logic cells and an embedded field programmable gate array (FPGA). The system and method provide error correction (EC) to enable a defective logic function implemented within an IC chip design to be replaced, wherein at least one embedded FPGA is provided in the IC chip to perform a logic function. If a defective logic function is identified in the IC design, the embedded FPGA is programmed to correctly perform the defective logic function. All inputs in an input cone of logic of the defective logic function are identified and are directed into the embedded FPGA, such that the embedded FPGA performs the logic function of the defective logic function. All outputs in an output cone of logic of the defective logic function are identified, and the output of the FPGA is directed to the output cone of logic of the defective logic function, such that logic EC is provided within the embedded FPGA structure of the IC chip.
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Cohn John M.
Reynolds Christopher B.
Ventrone Sebastian T.
Zuchowski Paul S.
International Business Machines - Corporation
LeStrange, Esq. Michael J.
Scully , Scott, Murphy & Presser, P.C.
Trimmings John P
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