Electrical computers and digital processing systems: processing – Processing control – Specialized instruction processing in support of testing,...
Patent
1997-11-26
2000-12-19
Eng, David Y.
Electrical computers and digital processing systems: processing
Processing control
Specialized instruction processing in support of testing,...
G06F 9000
Patent
active
061638404
ABSTRACT:
An apparatus is provided for sampling multiple concurretly executing instructions in a processor pipeline of a system. The pipeline has a plurality of processing stages. The apparatus identifies multiple selected when the instructions are fetched into a first stage of the pipeline. A subset of the the multiple selected instructions to execute concurrently in the pipeline. State information of the system is sampled while any of the multiple selected instructions are in any stage of the pipeline. Software is informed whenever all of the selected instructions leave the pipeline so that the software can read any of the state information.
REFERENCES:
patent: 4084231 (1978-04-01), Capozzi et al.
patent: 4481583 (1984-11-01), Mueller
patent: 4583165 (1986-04-01), Rosenfeld
patent: 4590550 (1986-05-01), Eilert et al.
patent: 4800521 (1989-01-01), Carter et al.
patent: 4821178 (1989-04-01), Levin et al.
patent: 4845615 (1989-07-01), Blasciak
patent: 5103394 (1992-04-01), Blasciak
patent: 5151981 (1992-09-01), Westcott et al.
patent: 5269017 (1993-12-01), Hayden et al.
patent: 5287508 (1994-02-01), Hejna, Jr. et al.
patent: 5301299 (1994-04-01), Pawlowski et al.
patent: 5321836 (1994-06-01), Crawford et al.
patent: 5339425 (1994-08-01), Vanderah et al.
patent: 5379427 (1995-01-01), Hiroshima
patent: 5379432 (1995-01-01), Orton
patent: 5388242 (1995-02-01), Jewett
patent: 5418973 (1995-05-01), Ellis et al.
patent: 5446876 (1995-08-01), Levine et al.
patent: 5450349 (1995-09-01), Brown, III et al.
patent: 5450586 (1995-09-01), Kuzara et al.
patent: 5450609 (1995-09-01), Schultz
patent: 5452440 (1995-09-01), Salsburg
patent: 5463775 (1995-10-01), DeWitt et al.
patent: 5479629 (1995-12-01), Angjelo et al.
patent: 5479652 (1995-12-01), Dreyer et al.
patent: 5485574 (1996-01-01), Bolosky et al.
patent: 5493673 (1996-02-01), Rindos et al.
patent: 5515538 (1996-05-01), Kleiman
patent: 5528753 (1996-06-01), Fortin
patent: 5530964 (1996-06-01), Alpert et al.
patent: 5537541 (1996-07-01), Wibecan
patent: 5572672 (1996-11-01), Dewitt et al.
patent: 5581482 (1996-12-01), Weidenman et al.
patent: 5581745 (1996-12-01), Muraoka et al.
patent: 5594741 (1997-01-01), Kinzelman
patent: 5594864 (1997-01-01), Trauben
patent: 5603004 (1997-02-01), Kurpanek et al.
patent: 5608892 (1997-03-01), Wakerly
patent: 5623627 (1997-04-01), Witt
patent: 5630157 (1997-05-01), Dwyer, III
patent: 5649136 (1997-07-01), Shen et al.
patent: 5651112 (1997-07-01), Matsuno et al.
patent: 5691920 (1997-11-01), Levine et al.
patent: 5748468 (1998-05-01), Notenboom et al.
patent: 5751945 (1998-05-01), Levine et al.
patent: 5765204 (1998-06-01), Bakke et al
patent: 5768500 (1998-06-01), Agrawal et al.
patent: 5774718 (1998-06-01), Aoshima et al.
patent: 5799143 (1998-08-01), Butt et al.
patent: 5802378 (1998-09-01), Arndt et al.
patent: 5802386 (1998-09-01), Kahle et al.
patent: 5802593 (1998-09-01), Grimsrud
patent: 5809450 (1998-09-01), Chrysos et al.
patent: 5854934 (1998-12-01), Hsu et al.
patent: 5857097 (1999-01-01), Henzinger et al.
patent: 5860018 (1999-01-01), Panwar
patent: 5862371 (1999-01-01), Levine et al.
patent: 5878208 (1999-03-01), Levine et al.
patent: 5884080 (1999-03-01), Blandy et al.
patent: 5922070 (1999-07-01), Swoboda et al.
patent: 5923872 (1999-07-01), Chrysos et al.
patent: 5944841 (1999-08-01), Christie
patent: 5964867 (1999-10-01), Anderson et al.
patent: 5987598 (1999-11-01), Levine et al.
patent: 6000044 (1999-12-01), Chrysos et al.
"Instruction Match Function for Processor Performance Monitoring"; IBM Technical Disclosure Bulletin, vol. 39, No. 12, Dec. 1996 (1996-12), pp. 119-121; XP000686036; ISSN: 0018-8689.
European Search Report dated Jan. 11, 2000; European Patent Application No. 98309672.8; 4 pages total.
Roth C. et al. "Performance Monitoring on The PowerPC.TM. 604 Microprocessor" Oct. 2, 1995, pp. 212-215.
IBM technical disclosure bulletin, US IBM Corp. "Automatic Program Reordering For Data References In Unified Cache" Apr. 4, 1996, vol. 39 No. 4.
Kay, J. and Lauder, P. "A Fair Share Scheduler," Communications of the ACM, vol. 31, No. 1, pp. 44-55, Jan., 1988.
Hellerstein, Joseph L., "Achieving Service Rate Objectives With Decay Usage Scheduling," IEEE Trans on Software Engineering, vol. 19, No. 8, pp. 813-825, Aug. 1993.
"Technique For Speculatively Sampling Performance Parameters," IBM TDB, vol. 37, No. 9, pp. 589-592, Sep. 1994.
Instruction Set Execution Frequency Estimation by Means of Program Counter Sampling, IBM Technical Disclosure Bulletin, 33:10a, p. 203.
"Processor Performance Monitoring with a Depiction of the Efficiency of the Cache Coherency Protocol of a Superscalar Microprocessor in a Symmetric Multiple Processor Environment," IBM TDB, vol. 40, n. 1, pp. 79-81, Jan. 1997.
Martonosi, M. et al., "MemSpy: Analyzing Memory System Bottlenecks In Programs," Performance. Evaluation Review, vol. 20, n. 1, pp. 1-12, Jun. 1992.
ProfileMe: hardware support for instruction-level profiling on out-of-order processors, Dean J. et al., Microarchitecutre, 1997. Proceedings, Thirtieth Annual IEEE/ACM International Symposium on, Dec. 1-3, 1997, pp. 292-302.
Exploiting Hardware Performance Counters with Flow and Context Sensitive Profiling, Ammons, G. et al., ACM, 1997.
Monitoring Program Behaviour on SUPRENUM, Siegle, M. et al. ACM, 1992.
Custer, "Inside Windows NT", Microsoft Press, p. 93.
Abraham et al., Predicting Load Latencies Using Cache Profiling, HPL-94-110, Nov. 1994, copyright Hewlett-Packard Co.
Anderson et al., Continuous Profiling: Where Have All The Cycles Gone? To be published in The Proceedings of the 16.sup.th ACM Symposium on Operating Systems Principles, copyright 1997 by the Assoc. for Computing Machinery.
Ball et al., Efficient Path Profiling, Published in Proceedings of MICRO-29, Dec. 2-4, 1996, in Paris, France, pp. 46-57. Copyright 1996 IEEE.
Bershad et al., Avoiding Conflict Misses Dynamically in Large Direct-Mapped Caches, Proceedings of the 6.sup.th International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 158-170, Oct. 4-7, 1994.
Cohn et al., Hot Cold Optimization of Large Windows/NT Applications, Proceedings of the 29.sup.th Annual International Symposium on Microarchitecture, pp. 80-89, Dec. 1996. Copyright 1996 IEEE.
Conte et al., Using Branch Handling Hardware to Support Profile-Driven Optimization, Proceedings of the 1994 27.sup.th Annual International Symposium on Microarchitecture, Nov. 30-Dec. 2, 1994, San Jose, Calif.
Conte et al., Accurate and Practical Profile-Driven Compilation Using the Profile Buffer, Proceedings of the 29.sup.th Annual International Symposium on Microarchitecture, pp. 36-45, Dec. 2-4, 1996.
Fisher, J.A., Global Code Generation for Instruction-Level Parallelism: Trace Scheduling-2, Hewlett-Packard Technical Report No. HPL-93-43, Jun., 1993. To be published by Springer-Verlag, London, UK.
Horowitz et al., Informing Memory Operations: Providing Memory Performance Feedback in Modern Processors, Proceedings of the 23.sup.rd Annual International Symposium on Computer Architecture, pp. 260-270, May 22-24, 1996.
Hwu et al., The Superblock: An Effective Technique for VLIW and Superscalar Compilation, Center for Reliable and High-Performance Computing, Univ. of Illinois, Urbana-Champaign, Illinois, 61801.
Romer et al., Dynamic Page Mapping Policies for Cache Conflict Resolution on Standard Hardware, Proceedings of the First Symposium for Operating Systems Design and Implementation, pp. 255-266, 1994.
Romer et al., Reducing TLB and Memory Overhead Using Online Superpage Promotion, Proceedings of the 22.sup.nd Annual International Symposium on Computer Architecture, pp. 176-187, Jun. 1995.
Tullsen et al., Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor, Proceedings of the 23.sup.rd Annual International Symposium on Computer Architecture, Philadelphia, PA, May, 1996.
Tullsen et al., Simultaneous Multithreading: Maximizing On-Chip Parallelism, Proceedings of the 22.sup.nd Annual International Symposium On Computer Architecture, Santa Margherita Li
Chrysos George Z.
Dean Jeffrey
Hicks James E.
Leibholz Daniel L.
McLellan Edward J.
Compaq Computer Corporation
Eng David Y.
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