Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – With lattice constant mismatch
Reexamination Certificate
2011-03-15
2011-03-15
Vu, Hung (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
With lattice constant mismatch
C257SE21632, C257SE27062
Reexamination Certificate
active
07906798
ABSTRACT:
A semiconductor device includes an NMOS transistor and a PMOS transistor. The NMOS transistor includes a channel area formed in a silicon substrate, a gate electrode formed on a gate insulating film in correspondence with the channel area, and a source area and a drain area formed in the silicon substrate having the channel area situated therebetween. The PMOS transistor includes another channel area formed in the silicon substrate, another gate electrode formed on another gate insulating film in correspondence with the other channel area, and another source area and another drain area formed in the silicon substrate having the other channel area situated therebetween. The gate electrode has first sidewall insulating films. The other gate electrode has second sidewall insulating films. The distance between the second sidewall insulating films and the silicon substrate is greater than the distance between the first sidewall insulating films and the silicon substrate.
REFERENCES:
patent: 5696012 (1997-12-01), Son
patent: 6727136 (2004-04-01), Buller et al.
patent: 7271414 (2007-09-01), Tamura et al.
patent: 7429775 (2008-09-01), Nayak et al.
patent: 2005/0093078 (2005-05-01), Chan et al.
patent: 2006/0281285 (2006-12-01), Kimoto
patent: 2005175378 (2005-06-01), None
patent: 2006-216604 (2006-08-01), None
patent: 0214468 (1999-08-01), None
Korean Office Action mailed date Aug. 12, 2009, issued in corresponding Korean Patent Application No. 10-2007-0128783.
G.H. Buh et al; “Interface States as an Activate Component for 20 nm Gate-Length Planar MOSFET with ElectroStatic Channel Extension (ESCE)”; IEEE IEDM 2005.
Ohta Hiroyuki
Ookoshi Katsuaki
Fujitsu Patent Center
Fujitsu Semiconductor Limited
Vu Hung
Webb Vernon P
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