Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2008-07-15
2008-07-15
Pham, Thanhha (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S593000, C257SE21655
Reexamination Certificate
active
07399673
ABSTRACT:
In a charge-trapping device having an array of memory cells, which are controlled by word lines buried in trenches within a substrate, further trenches are formed parallel to said word lines within said substrate. These subdivide diffusion regions adjacent to the word lines into each a first diffusion region adjacent to a first trench of a first charge-trapping memory cell and a second diffusion region adjacent to a first trench of a second charge-trapping memory cell. The depth of the further trench is sufficient to impede hot charge carrier exchange between neighboring memory cells. For this purpose the further trenches are filled with dielectric material, e.g., an oxide. The depth of the further trenches may be, e.g., half of that of the word line trench, and the width may, e.g., amount to 15-20 nm.
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Infineon - Technologies AG
Pham Thanhha
Slater & Matsil L.L.P.
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