Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2011-03-29
2011-03-29
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S733000, C714S727000
Reexamination Certificate
active
07917824
ABSTRACT:
Scan architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.
REFERENCES:
patent: 5254942 (1993-10-01), D'Souza et al.
patent: 5355369 (1994-10-01), Greenberger et al.
patent: 5485466 (1996-01-01), Lyon et al.
patent: 6278307 (2001-08-01), El-Kik
Girard, P.; Guiller, L.; Landrault, C.; Pravossoudovitch, S.; , “Low power BIST design by hypergraph partitioning: methodology and architectures,” Test Conference, 2000. Proceedings. International , vol., No., pp. 652-661, 2000 doi: 10.1109/TEST.2000.894260 URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=894260&isnumber=19342.
Schober, V.; Kiel, T.; , “An asynchronous scan path concept for micropipelines using the bundled data convention,” Test Conference, 1996. Proceedings., International , vol., No., pp. 225-231, Oct. 20-25, 1996 doi: 10.1109/TEST.1996.556965 URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=556965&isnumber=12091.
Nadeau-Dostie, B.; Burek, D.; Hassan, A.S.M.; , “ScanBist: a multifrequency scan-based BIST method,” Design & Test of Computers, IEEE , vol. 11, No. 1, pp. 7-17, Spring 1994 doi: 10.1109/54.262318 URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=262318&isnumber=6607.
Bassuk Lawrence J.
Brady W. James
Britt Cynthia
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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