Pattern controlled IC layout

Electronic digital logic circuitry – Significant integrated structure – layout – or layout...

Reexamination Certificate

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C326S104000, C257S206000

Reexamination Certificate

active

07969199

ABSTRACT:
The invention provides a reduced complexity layout style based on applying a limited set of changes to an underlying repeated base template. With the templates properly defined in accordance with the characteristic features disclosed, the invention enables efficient implementation of logic circuitry, with a dramatic reduction in the pattern complexity (or number of unique layout patterns at each mask level) for realistically sized designs. This reduction in pattern complexity that the invention provides is particularly important for advanced and emerging semiconductor processes, because it enables effective use of SMO and full-chip mask optimization.

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