Method of fabricating a transistor with a dielectric underlayer

Details Method of fabricating a transistor with a dielectric underlayer Method of fabricating a transistor with a dielectric underlayer

1999-01-14

2000-12-19

Trinh, Michael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438155, 438164, 438300, 438595, H01L 21336, H01L 2100

Patent

active

061626880

ABSTRACT:
A method is provided for fabricating a transistor, the method including forming a dielectric layer above a structure, forming a first polysilicon layer above the dielectric layer and forming a sacrificial region above the first polysilicon layer. The method also includes forming a second polysilicon layer above the first polysilicon layer and adjacent the sacrificial region. The method further includes removing the sacrificial region to form an opening in the second polysilicon layer, the opening having sidewalls, and forming dielectric spacers on the sidewalls of the opening. In addition, the method includes forming a gate dielectric within the opening above the first polysilicon layer and forming a gate conductor above the gate dielectric.

REFERENCES:
patent: 4677735 (1987-07-01), Malhi
patent: 5700700 (1997-12-01), Hwang
patent: 5705405 (1998-01-01), Cunningham
patent: 5904508 (1999-05-01), Codama et al.
patent: 6074919 (2000-06-01), Gardner et al.
patent: 6074920 (2000-06-01), Houston
patent: 6103559 (2000-08-01), Gardner et al.

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