DRAM tunneling access transistor

Details DRAM tunneling access transistor DRAM tunneling access transistor

2011-07-19

2011-07-19

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S177000

Reexamination Certificate

active

07983070

ABSTRACT:
In one embodiment, a first transistor is comprised of a first p+ source region doped in an n-well in the substrate and a first n+ drain region doped on one side at the top of the pillar. A second transistor is comprised of a second p+ source region doped into the second side of the top of the pillar and serially coupled to the top drain region for the first transistor. A second n+ drain region is doped into the substrate adjacent the pillar. Ultra-thin body layer run along each pillar sidewall between their respective active regions. A gate structure is formed along the pillar sidewalls and over the body layers. The transistors operate by electron tunneling from the source valence band to the gate bias-induced n-type channels, along the ultra-thin silicon bodies, thus resulting in a drain current.

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