Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2011-08-30
2011-08-30
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
08010857
ABSTRACT:
Scan testing of plural target electrical circuits, such as circuits1through N, becomes accelerated by using the scan test response data output from one circuit, such as circuit1,as the scan test stimulus data for another circuit, such as circuit2.After reset, a scan path captures the output response data from the reset stimulus from all circuits. A tester then shifts the captured data only the length of the first circuit's scan path while loading the first circuit's scan path with new test stimulus data. The new response data from all the circuits then is captured in the scan path. This shift and capture cycle is repeated until the first circuit is tested. The first circuit is then disabled and any remaining stimulus data is applied to the second circuit. This process is repeated until all the circuits are tested. A data retaining boundary scan cell used in the scan testing connects the output of an additional multiplexer as the input to a boundary cell. The inputs of the additional multiplexer connect to the data input and data output of the boundary cell.
REFERENCES:
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patent: 5596584 (1997-01-01), Warren
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Ono, T.; Wakui, K.; Hikima, H.; Nakamura, Y.; Yoshida, M.;, “Integrated and automated design-for-testability implementation for cell-based ICs,” Test Symposium, 1997. (ATS '97) Proceedings., Sixth Asian, vol., no., pp. 122-125, Nov. 17-19, 1997 doi: 10.1109/ATS. 1997.643946.
Bassuk Lawrence J.
Brady W. James
Britt Cynthia
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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