Scan testable register file

Details Scan testable register file Scan testable register file

2011-03-15

2011-03-15

Tabone, Jr., John J (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S718000, C714S726000, C714S731000, C365S200000

Reexamination Certificate

active

07908535

ABSTRACT:
Memory compiler engineers often focus on the efficient implementation of the largest possible memory configurations for each memory type. The overhead of test and control circuitry within memory implementations is usually amortized across a large number of storage bits. Unfortunately, test structures generally do not scale down with decreasing memory sizes, creating a large area penalty for a design with numerous small memories. One solution is a scannable register file (SRF) architecture using scannable latch bit-cells laid out using a standard cell layout/power template. All sub-cells can be placed in standard cell rows and utilize standard cell power straps. Non-SRF standard cells can be abutted on all sides, placement keep-out regions are not needed. Metal utilization is usually limited to first three metallization layers. The bit-cell is much larger than standard compiled memory bit cells, but has no overhead beyond address decode, word-line drivers, and read-write data latches.

REFERENCES:
patent: 4493077 (1985-01-01), Agrawal et al.
patent: 5631911 (1997-05-01), Whetsel, Jr.
patent: 5917832 (1999-06-01), Baeg et al.
patent: 5926487 (1999-07-01), Chappell et al.
patent: 5961653 (1999-10-01), Kalter et al.
patent: 6055649 (2000-04-01), Deao et al.
patent: 6611934 (2003-08-01), Whetsel, Jr.
patent: 6763485 (2004-07-01), Whetsel
patent: 6925590 (2005-08-01), Campbell
patent: 7383480 (2008-06-01), Martin et al.
patent: 7516379 (2009-04-01), Rohrbaugh et al.
patent: 2003/0131295 (2003-07-01), Berry, Jr. et al.
patent: 2003/0200493 (2003-10-01), Campbell
patent: 2004/0250165 (2004-12-01), Tanizaki
patent: 2005/0010832 (2005-01-01), Caswell et al.
patent: 2005/0210179 (2005-09-01), Wamsley et al.
patent: 2005/0235185 (2005-10-01), Campbell
patent: 2010/0153796 (2010-06-01), Rachapalli
Yano et al., Memory Array Testing through a Scannable Configuration, 1997, IEEE, pp. 87-94.
Yano, Unified Scan Design with Scannable Memory Arrays, Nov. 1995, IEEE, pp. 153-159.
Seuring, Combining Scan Test and Built-in Self Test, Jun. 26, 2006, Journal of Electronic Testing: Theory and Applications, pp. 297-299.
Vorisek et al., At-speed Testing of SOC ICs, 2004, IEEE. pp. 1-6.

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