Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2011-01-11
2011-01-11
Maldonado, Julio J (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S276000, C438S287000, C438S289000, C257SE21633, C257SE21639
Reexamination Certificate
active
07867839
ABSTRACT:
Disclosed are embodiments of a p-type, silicon germanium (SiGe), high-k dielectric-metal gate, metal oxide semiconductor field effect transistor (PFET) having an optimal threshold voltage (Vt), a complementary metal oxide semiconductor (CMOS) device that includes the PFET and methods of forming both the PFET alone and the CMOS device. The embodiments incorporate negatively charged ions (e.g., fluorine (F), chlorine (Cl), bromine (Br), iodine (I), etc.) into the high-k gate dielectric material of the PFET only so as to selectively adjust the negative Vt of the PFET (i.e., so as to reduce the negative Vt of the PFET).
REFERENCES:
patent: 6972224 (2005-12-01), Gilmer et al.
patent: 7138692 (2006-11-01), Tamura et al.
patent: 2008/0079086 (2008-04-01), Jung et al.
patent: 2009/0068812 (2009-03-01), Prall et al.
Chen Xiangdong
Lee Jong Ho
Li Weipeng
Park Dae-gyu
Stein Kenneth J.
Cai, Esq. Yuanmin
Gibb I.P. Law Firm LLC
International Business Machines - Corporation
Maldonado Julio J
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