Resynchronization memory in series/parallel with...

Details Resynchronization memory in series/parallel with... Resynchronization memory in series/parallel with...

2011-07-05

2011-07-05

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S731000, C714S729000

Reexamination Certificate

active

07975196

ABSTRACT:
An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A dedicated scan cell has a functional data output separate from a test data output. Shared scan cells each have a combined output for functional data and test data. The shared scan cells are coupled in series. The test data input of the first shared scan cell is connected to the test data output of the dedicated scan cell. The combined output of one shared scan cell is coupled to the test data input lead of another shared scan cell. The multiplexer has an input coupled to the test data output, an input connected to the combined output lead of the last shared scan cell in the series, and an output connected in the scan path.

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Ming-Der Shieh; Chin-Long Wey; Fisher, P.D.;, “A scan design for asynchronous sequential logic circuits using SR-latches,” Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on, vol., no., pp. 1300-1303 vol. 2, Aug. 16-18, 1993 doi: 10.1109/MWSCAS. 1993.343339.

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