Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2011-04-19
2011-04-19
Landau, Matthew C (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S108000, C438S618000, C438S640000, C257SE21575
Reexamination Certificate
active
07927999
ABSTRACT:
The semiconductor device1includes interconnect layers10, 20, an IC chip30, via plugs42, 44, a seal resin50, and solder balls60. The interconnect layer10includes a via plug42. An end face of the via plug42on the side of the interconnect layer20is smaller in area than the opposite end face, i.e. the end face on the side of the IC chip30. An end face of the via plug44on the side of the interconnect layer10is smaller in area than the opposite end face, i.e. the end face on the side of the solder balls60. The thermal decomposition temperature of the insulating resin14constituting the interconnect layer10is higher than that of the insulating resin24constituting the interconnect layer20.
REFERENCES:
patent: 4497864 (1985-02-01), Ryoke et al.
patent: 4788097 (1988-11-01), Ohara et al.
patent: 4861854 (1989-08-01), Sugio et al.
patent: 5284899 (1994-02-01), Morishige et al.
patent: 6406942 (2002-06-01), Honda
patent: 6833895 (2004-12-01), Ishii et al.
patent: 6902950 (2005-06-01), Ma et al.
patent: 7452797 (2008-11-01), Kukimoto et al.
patent: 2002/0054471 (2002-05-01), Adae-Amoakoh et al.
patent: 2003/0202142 (2003-10-01), Ishii et al.
patent: 2003/0230813 (2003-12-01), Hirano et al.
patent: 2004/0090756 (2004-05-01), Ho et al.
patent: 2005/0056942 (2005-03-01), Pogge et al.
patent: 2006/0043570 (2006-03-01), Muramatsu et al.
patent: 2006/0226556 (2006-10-01), Kurita et al.
patent: 2007/0026662 (2007-02-01), Kawano et al.
patent: 2007/0169886 (2007-07-01), Watanabe et al.
patent: 2007/0184604 (2007-08-01), Honda
patent: 2007/0241464 (2007-10-01), Pendse et al.
patent: 2008/0079163 (2008-04-01), Kurita et al.
patent: 2008/0312383 (2008-12-01), Tanaka et al.
patent: 2009/0008765 (2009-01-01), Yamano et al.
patent: 62-229899 (1987-10-01), None
patent: 01-143394 (1989-06-01), None
patent: 11126978 (1999-11-01), None
patent: 2001177010 (2001-06-01), None
patent: 2002-343931 (2002-11-01), None
patent: 2002343931 (2002-11-01), None
patent: 2003-309215 (2003-10-01), None
patent: 2004-039867 (2004-02-01), None
patent: 200439867 (2004-02-01), None
patent: 2004-265967 (2004-09-01), None
patent: 2004265967 (2004-09-01), None
patent: 2005-063987 (2005-03-01), None
patent: 96-19829 (1996-06-01), None
Song, et al. “Thermal Decomposition Characteristics of DGEBA/MDA/GN System for Insulating Materials” Sep. 1998, Proceedings of 1998 International Symposium on Electrical Insulating Materials, p. 286.
Semiconductor OneSource, “Interconnect”, http://www.semi1source.com/glossary/default.asp?searchterm=interconnect.
Japanese Official Action—2005-109993—Sep. 16, 2010.
Kawano Masaya
Kurita Yoichiro
Soejima Koji
Landau Matthew C
Nicely Joseph C
Renesas Electronics Corporation
Young & Thompson
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