Manufacturing process of a vertical-conduction MISFET device...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S217000, C438S276000, C438S287000, C257S335000, C257S328000, C257S346000, C257S411000, C257SE29256, C257SE21417

Reexamination Certificate

active

07968412

ABSTRACT:
According to an embodiment of a method for manufacturing a MISFET device, in a semiconductor wafer, a semiconductor layer is formed, having a first type of conductivity and a first level of doping. A first body region and a second body region, having a second type of conductivity, opposite to the first type of conductivity, and an enriched region, extending between the first and second body regions are formed in the semiconductor layer. The enriched region has the first type of conductivity and a second level of doping, higher than the first level of doping. Moreover, a gate electrode is formed over the enriched region and over part of the first and second body regions, and a dielectric gate structure is formed between the gate electrode and the semiconductor layer, the dielectric gate structure having a larger thickness on the enriched region and a smaller thickness on the first and second body regions. To form the enriched region, a first conductive layer is made on the semiconductor layer, an enrichment opening is formed in the first conductive layer, and a dopant species is introduced into the semiconductor layer through the enrichment opening. Furthermore, the formation of the dielectric gate structure envisages filling the enrichment opening with dielectric material, prior to forming the first body region and the second body region.

REFERENCES:
patent: 4199774 (1980-04-01), Plummer
patent: 4376286 (1983-03-01), Lidov et al.
patent: 4974059 (1990-11-01), Kinzer
patent: 6049104 (2000-04-01), Hshieh et al.
patent: 6362036 (2002-03-01), Chiozzi et al.
patent: 6992353 (2006-01-01), Wu
patent: 7067363 (2006-06-01), Magri′ et al.
patent: 2003/0057478 (2003-03-01), Yun et al.
patent: 2004/0164346 (2004-08-01), Venkatraman
patent: 2005/0139906 (2005-06-01), Magri′ et al.
patent: 2007/0064362 (2007-03-01), Migliavacca
patent: 0 586 835 (1994-03-01), None
patent: 0 747 968 (1996-12-01), None
patent: 1 313 147 (2003-05-01), None
patent: 1 455 397 (2004-09-01), None
patent: 05299658 (1993-11-01), None
patent: 07221296 (1995-08-01), None
patent: 09102506 (1997-04-01), None
patent: 10335643 (1998-12-01), None
patent: 2006114376 (2006-11-01), None
International Search Report, for International Patent Application No. PCT/EP2006/061664, dated Jul. 17, 2006.
European Search Report for European Patent Application No. EP05425260, dated Feb. 20, 2006.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Manufacturing process of a vertical-conduction MISFET device... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Manufacturing process of a vertical-conduction MISFET device..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Manufacturing process of a vertical-conduction MISFET device... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2652328

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.