Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2011-01-11
2011-01-11
Nguyen, Thanh (Department: 2893)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S301000, C438S303000, C438S592000, C257SE29255, C257SE21438
Reexamination Certificate
active
07867863
ABSTRACT:
A transistor structure includes a semiconductor substrate with a first surface, a diffusion region at the first surface of the substrate, a sacrificial gate formed on the diffusion region, and insulating side walls formed adjacent to the sacrificial gate. A metal gate is formed by etching out the sacrificial gate and filling in the space between the insulating side walls with gate metals. Silicided source and drain contacts are formed over the diffusion region between the side walls of two adjacent aluminum gates. One or more oxide layers are formed over the substrate. Vias are formed in the oxide layers by plasma etching to expose the silicided source and drain contacts, which simultaneously oxidizes the aluminum gate metal. A first metal is selectively formed over the silicided contact by electroless deposition, but does not deposit on the oxidized aluminum gate.
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Pan, James et al., “Novel Approach to Reduce Source/Drain Series and Contact Resistance in High-Performance UTSOICMOS Devices Using Selective Electrodeless CoWP or CoB Process”, IEEE Electron Device Letters, vol. 28, No. 8, (Aug. 2007), pp. 691-693.
Pan, James et al., “Novel Approach to Reduce Source/Drain Series Resistance in High Performance CMOS Devices Using Self-Aligned CoWP Process for 45nm Node UTSOI transistors with 20nm Gate Length”, 2006 Symposium on VLSI Technology Digest of Technical Papers; 2006 IEEE, (Aug. 2006), 2 pgs.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Nguyen Thanh
LandOfFree
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