Cache sharing based thread control

Details Cache sharing based thread control Cache sharing based thread control

2011-02-22

2011-02-22

Chan, Eddie P (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Reexamination Certificate

active

07895415

ABSTRACT:
Apparatus and computing systems associated with cache sharing based thread control are described. One embodiment includes a memory to store a thread control instruction and a processor to execute the thread control instruction. The processor is coupled to the memory. The processor includes a first unit to dynamically determine a cache sharing behavior between threads in a multi-threaded computing system and a second unit to dynamically control the composition of a set of threads in the multi-threaded computing system. The composition of the set of threads is based, at least in part, on thread affinity as exhibited by cache-sharing behavior. The thread control instruction controls the operation of the first unit and the second unit.

REFERENCES:
Suh et. al; A New Memory Monitoring Scheme for Memory-Aware Scheduling and Partitioning; 2002; IEEE.
Suh et al.; Dynamic Cache Partioning for Simultaneous Multithreading Systems; 2001; CSAIL.
Kim et al.; Fair Cache Sharing and Partioning in a Chip Multiprocessor Architecture; 2004; PACT.
Settle et al.; A Dynamically Reconfigurable Cache for Multithreaded Processors; Apr. 2006.

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