Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2011-04-12
2011-04-12
Ho, Tu-Tu V (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S260000, C257S319000, C257SE29300, C257SE29112, C257SE21422, C257SE21179
Reexamination Certificate
active
07923328
ABSTRACT:
A non-volatile memory cell including a substrate in which is formed a source region and a drain region defining a channel region between the source region and the drain region is provided. The non-volatile memory cell further includes a select gate structure overlying a first portion of the channel region. The non-volatile memory cell further includes a control gate structure formed overlying a second portion of the channel region, wherein the control gate structure includes a nanocrystal stack having a height, wherein the control gate structure has a convex shape in a corner region formed at an intersection of a first plane substantially parallel to a top surface of the substrate and a second plane substantially parallel to a side surface of the control gate structure, wherein a ratio of radius of the control gate structure in the corner region to the height of the nanocrystal stack is at least 0.5.
REFERENCES:
patent: 6229176 (2001-05-01), Hsieh et al.
patent: 6828618 (2004-12-01), Baker et al.
patent: 6838725 (2005-01-01), Lin et al.
patent: 7544980 (2009-06-01), Chindalore et al.
patent: 7727829 (2010-06-01), Trivedi et al.
patent: 7737018 (2010-06-01), Mathew et al.
patent: 2005/0082601 (2005-04-01), Chu et al.
patent: 2005/0085039 (2005-04-01), Yasui et al.
patent: 2005/0199940 (2005-09-01), Mine et al.
patent: 2007/0029607 (2007-02-01), Kouznetzov
patent: 2007/0093010 (2007-04-01), Mathew et al.
Palestri et al; “Effect of the gap size on the SSI efficiency of split-gate memory cells”; IEEE Transactions on Electron Devices, vol. 53, Issue 3, Mar. 2006 pp. 488-493.
Non-Published U.S. Appl. No. 11/671,809, filed Feb. 6, 2007, showing Brian A. Winstead as the first named inventor.
Non-Published U.S. Appl. No. 12/103,451, filed Apr. 15, 2008, showing Sung-Taeg Kang as the first named inventor.
White Ted R.
Winstead Brian A.
Clingan, Jr. James L.
Freescale Semiconductor Inc.
Ho Tu-Tu V
Singh Ranjeev
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