Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2011-06-14
2011-06-14
Jackson, Jr., Jerome (Department: 2815)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257SE21442, C438S270000
Reexamination Certificate
active
07960232
ABSTRACT:
By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping and “wrapped” gates can be used in conjunction with the segmented channel regions to further enhance device performance.
REFERENCES:
patent: 6593176 (2003-07-01), Dennison
patent: 6706571 (2004-03-01), Yu et al.
patent: 6812508 (2004-11-01), Fukumi
patent: 7714397 (2010-05-01), Hareland et al.
patent: 2004/0099925 (2004-05-01), Poveda
patent: 2004/0108559 (2004-06-01), Sugii et al.
patent: 2004/0217448 (2004-11-01), Kumagai et al.
patent: 2005/0023569 (2005-02-01), Yang
patent: 2005/0056892 (2005-03-01), Seliskar
patent: 2005/0202604 (2005-09-01), Cheng et al.
patent: 2005/0224800 (2005-10-01), Lindert et al.
patent: 2005/0224875 (2005-10-01), Anderson et al.
patent: 2005/0224890 (2005-10-01), Bernstein et al.
patent: 2005/0239254 (2005-10-01), Chi et al.
patent: 2005/0280121 (2005-12-01), Doris et al.
patent: 2005/0285186 (2005-12-01), Fujiwara
patent: 2006/0113603 (2006-06-01), Currie
patent: 2007/0292996 (2007-12-01), Abadeer et al.
Quirk et al. Semiconductor Manufacturing Technology, 2001, Prentice Hall, pp. 4-7 and 390-393.
Brigham Young University, Crystal Planes in Semiconductors, 2010, http://cleanroom.byu.edu/EW—orientation.phtml, pp. 1-2.
King Tsu-Jae
Moroz Victor
Bever Hoffman & Harms LLP
Budd Paul A
Harms Jeanette S.
Jackson, Jr. Jerome
Synopsys Inc.
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