Planarization method using hybrid oxide and polysilicon CMP

Details Planarization method using hybrid oxide and polysilicon CMP Planarization method using hybrid oxide and polysilicon CMP

2011-07-05

2011-07-05

Deo, Duy-Vu N (Department: 1713)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S691000, C438S692000, C438S693000

Reexamination Certificate

active

07972962

ABSTRACT:
A method of planarizing a semiconductor device is provided. The semiconductor device includes a substrate, first and second components provided on the surface of the substrate, and a first material provided between and above the first and second components. The first component has a height greater than a height of the second component. The method includes performing a first polishing step on the semiconductor device to remove the first material above a top surface of the first component, to remove the first material above a top surface of the second component, and to level the top surface of the first component. The method also includes performing a second polishing step on the semiconductor device to planarize the top surfaces of the first and second components.

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Co-pending U.S. Appl. No. 11/551,390, filed Oct. 20, 2006 entitled “Planarization method using hybrid oxide and polysilicon cmp” by David Matsumoto et al., 38 pages.

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