Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-09-13
2001-11-27
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S253000, C438S255000, C438S256000, C438S396000, C438S398000
Reexamination Certificate
active
06323080
ABSTRACT:
TECHNICAL FIELD
The invention pertains to semiconductor capacitor constructions and to methods of forming semiconductor capacitor constructions. The invention also pertains to semiconductor conductive contact constructions and to methods of forming semiconductor conductive contacts. The invention is thought to have particular significance in application to methods of forming dynamic random access memory (DRAM) cell structures, to DRAM cell structures, and to integrated circuitry incorporating DRAM cell structures.
BACKGROUND OF THE INVENTION
A commonly used semiconductor memory device is a DRAM cell. A DRAM cell generally consists of a capacitor coupled through a transistor to a bitline. A continuous challenge in the semiconductor industry is to increase DRAM circuit density. Accordingly, there is a continuous effort to decrease the size of memory cell components. A limitation on the minimal size of cell components is impacted by the resolution of a photolithographic etch during fabrication of the cell components. Although this resolution is generally improving, at any given time there is a minimum photolithographic feature dimension of which a given fabrication process is capable. It would be desirable to form DRAM components having at least some portion with a cross-sectional dimension of less than a given minimum capable photolithographic feature dimension.
Another continuous trend in the semiconductor industry is to minimize processing steps. Accordingly, it is desirable to utilize common steps for the formation of separate DRAM components. For instance, it is desirable to utilize common steps for the formation of DRAM capacitor structures and DRAM bitline contacts.
A semiconductor wafer fragment
10
is illustrated in
FIG. 1
showing prior art DRAM array
83
. Wafer fragment
10
comprises a semiconductive material
12
, field oxide regions
14
, and wordlines
24
and
26
. Wordlines
24
and
26
comprise a gate oxide layer
16
, a polysilicon layer
18
, a silicide layer
20
and a silicon oxide layer
22
. Silicide layer
20
comprises a refractory metal silicide, such as tungsten silicide, and polysilicon layer
18
typically comprises polysilicon doped with a conductivity enhancing dopant. Nitride spacers
30
are laterally adjacent wordlines
24
and
26
.
Electrical node locations
25
,
27
and
29
are between wordlines
24
and
26
and are electrically connected by transistor gates comprised by wordlines
24
and
26
. Node locations
25
,
27
and
29
are diffusion regions formed within semiconductive material
12
.
A borophosphosilicate glass (BPSG) layer
34
is over semiconductive material
12
and wordlines
24
and
26
. An oxide layer
32
is provided between BPSG layer
34
and material
12
. Oxide layer
32
inhibits diffusion of phosphorus from BPSG layer
34
into underlying materials.
Conductive pedestals
54
,
55
and
56
extend through BPSG layer
34
to node locations
25
,
27
and
29
, respectively. Capacitor constructions
62
and
64
contact upper surfaces of pedestals
54
and
56
, respectively. Capacitor constructions
62
and
64
comprise a storage node layer
66
, a dielectric layer
68
, and a cell plate layer
70
. Dielectric layer
68
comprises an electrically insulative layer, such as silicon nitride. Cell plate layer
70
comprises conductively doped polysilicon, and may alternatively be referred to as a cell layer
70
. Storage node layer
66
comprises conductively doped hemispherical grain polysilicon.
A conductive bitline plug
75
contacts an upper surface of pedestal
55
. Bitline plug
75
may comprise, for example, tungsten. Together, bitline plug
75
and pedestal
55
comprise a bitline contact
77
.
A bitline
76
extends over capacitors
62
and
64
and in electrical connection with bitline contact
77
. Bitline
76
may comprise, for example, aluminum.
The capacitors
62
and
64
are electrically connected to bitline contact
77
through transistor gates comprised by wordlines
26
. A first DRAM cell
79
comprises capacitor
62
electrically connected to bitline
76
through a wordline
26
and bitline contact
77
. A second DRAM cell
81
comprises capacitor
64
electrically connected to bitline
76
through wordline a
26
and bitline contact
77
. DRAM array
83
comprises first and second DRAM cells
79
and
81
.
SUMMARY OF THE INVENTION
The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; methods of forming capacitor and bitline constructions; DRAM memory cell constructions; capacitor constructions; capacitor and bitline constructions, conductive contact constructions, and integrated circuitry.
In one aspect, the invention includes a method of forming a capacitor storage node in a shape of a vertically elongated stem underlying a cap, the cap having a first cross-sectional dimension of equal to or greater than a minimum capable photolithographic feature dimension of a fabrication process, the stem having a second cross-sectional dimension of less than the first cross-sectional dimension.
In another aspect, the invention includes a capacitor construction comprising an electrically conductive pedestal which in lateral cross-section has a first lateral surface and a second lateral surface laterally opposing the first lateral surface; an inner electrically conductive layer against the first lateral surface and the second lateral surface; a first electrically insulative layer laterally adjacent the first and second lateral surfaces and laterally against the inner electrically conductive layer; an outer electrically conductive layer laterally adjacent the first and second lateral surfaces and laterally against the first electrically insulative layer; and a second electrically insulative layer laterally adjacent the first and second lateral surfaces and laterally outward of the outer conductive layer.
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Sakao, M., “A Capacitor-Over-Bit-Line (COB) Cell With A Hemispherical-Grain Storage Node For 64Mb DRAMs”, 1990 IEEE, pp. 27.3.1-27.3.4.
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Elms Richard
Luu Pho
Micro)n Technology, Inc.
Wells, St. John, Roberts Gregory & Matkin P.S.
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