Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With structure for mounting semiconductor chip to lead frame
Reexamination Certificate
1995-04-19
2001-11-06
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With structure for mounting semiconductor chip to lead frame
C257S666000
Reexamination Certificate
active
06313519
ABSTRACT:
TECHNICAL FIELD
The invention relates to the packaging of microelectronic circuits and, more particularly, to wire bonding dies to lead frames or the like.
BACKGROUND
There are various techniques of packaging a semiconductor die (microelectronic circuit), such as in a ceramic package, on a printed wiring board, in a plastic molded body, or on a tape. The latter two (plastic molded, tape) are representative of packaging techniques that employ lead frames. A lead frame is a generally planar layer of conductive material, patterned to have a plurality of conductor lines (lead fingers) radiating from a central area where the semiconductor die is located. For ceramic and printed wiring board packages, there is generally an analogous pattern of conductors on a insulating substrate (e.g., ceramic, FR4).
Irrespective of the type of package, the die must be connected to the inner ends of the lead fingers. One well-known way to effect this connection is by using bond wires attached at one end to bond pads on the die, and attached at their other end to the inner ends of the lead fingers. Bond wires are on the order of one thousandth of an inch, or less, in diameter. Bond pads are on the order of a few thousandths of an inch, spaced from one another on the order of one thousandth of an inch. Evidently, when many bond wires are connected to a die, this is a very crowded situation, and there is the possibility of these bond wires shorting against one another, breaking, and other related problems. This problem is exacerbated in plastic molded packaging, wherein a die is mounted to a lead frame, wire bonded thereto, inserted into a mold, and covered with plastic. The influx of plastic into the mold can cause movement of the closely-spaced bond wires, resulting in a defective packaged component. Coming this late in the process (during packaging), defects due to bond failure are generally irreversible and expensive.
The trend in microelectronics is to use smaller, denser semiconductor chips (dies) which have more functionality and which require more input/output (I/O) connections. Generally, each I/O connection requires a bond wire. It is therefore becoming increasingly difficult to package such chips (dies), especially in plastic packages, due to lead frame and bonding limitations.
FIGS. 1 and 2
illustrate a conventional technique of bonding a die
10
to a lead frame
13
, such as for plastic packaging. Only a relevant, inner portion of the lead frame is shown in these illustrations. The lead frame
13
includes a plurality of conductive lines (lead fingers)
14
arranged in a generally radial pattern from a central area. The lead frame
13
further includes a die paddle
12
, within the central area, and upon which rests the die
10
. The die paddle
12
is preferably somewhat larger (in area) than the die. Tiebars
15
extend radially outward from the four corners of the die paddle
12
to an outer structure of the lead frame (not shown), to support the die paddle. As best viewed in the cross-section of
FIG. 2
(tiebars omitted from this view), the die paddle
12
is depressed below the plane of the lead fingers
14
. This is a fairly common practice, for plastic packaging (transfer molding). In
FIG. 1
, there are illustrated two of many bond wires
16
, extending at one end
16
a
from a bond pad on a peripheral portion of the top face
11
of the die
10
to another end
16
b
connected to inner ends
14
a
of the lead fingers
14
. As mentioned above, there may be hundreds of such bond wires, closely spaced, and subject to deformation during the plastic molding process.
If one is working at the lowest possible limit of lead resolution and spacing, the only way to accommodate more leads
14
is to move them further away from the chip—in other words to increase the gap between the die and the inner ends of the lead fingers. (As illustrated in
FIG. 1
, the lead fingers radiate, or spread out, from the central area containing the die. By terminating the inner ends of the lead fingers at a greater distance from the die, they are inherently further apart from one another.)
By moving the lead fingers further away from the die, it is evident that the bond wires need to be longer. Returning to
FIG. 2
, it is evident that the bond wires span a “gap” between the die
10
and the inner ends of the lead fingers
14
. The bigger the gap, the longer the bond wires. Longer bond wires simply exacerbate the aforementioned problems of shorting, breaking, etc. Due to mechanical and molding considerations, the length of the bond wires
16
is the limiting factor in how far back one can position the leads. The maximum permissible single span of bond wire is on the order of 3-5 millimeters (mm), depending upon the application. Viewed another way, mechanical considerations vis-a-vis the (length of the) bond wires tend to limit the number of lead fingers, hence the I/O count, of a semiconductor device. This certainly seems antithetical in this day and age of miniaturization.
SUMMARY
It is therefore an object of the present invention to provide an improved technique for wire bonding, which permits the use of a greater number of lead fingers, hence a greater I/O count, irrespective of a large gap between the lead fingers and the die.
It is a further object of the present invention to enable longer lengths of bond wire to be used, thereby enabling the lead frame (fingers) to be positioned further away from the chip (die) and enable more leads (fingers) to be accommodated.
According to the present invention, a support means is provided between, preferably approximately midway between, the die and the inner ends of the lead fingers of a lead frame. Intermediate portions of the wires are bonded, or tacked, to an upper surface of the support means. In this manner, the length of the bond wires can be doubled, and the lead fingers can be commensurately further from the die, while avoiding the problems associated with long bond wires.
The support means is preferably a continuous element extending “circumferentially” (in a square sense of the term) around the chip (die). In a sense, the support means forms a “way station” for stabilizing the bond wires.
The upper surface of the support means is preferably provided with bond pads, to which the intermediate portions of the bond wires are bonded.
Alternatively, the support means can be formed of an insulating material, and the intermediate portions of the bond wires tacked thereto with a suitable adhesive.
Alternatively, the support means can be provided with a plurality of notches on its upper surface, each notch retaining and locating the intermediate portion of a respective bond wire.
Other objects, features and advantages of the invention will become apparent in light of the following description thereof.
REFERENCES:
patent: 4771330 (1988-09-01), Long
patent: 4903114 (1990-02-01), Hoki et al.
patent: 5168368 (1992-12-01), Gow, 3rd et al.
patent: 0078606 (1983-05-01), None
patent: 0247644 (1987-12-01), None
patent: 0259222 (1988-03-01), None
patent: 0311513 (1990-10-01), None
patent: 0513591 (1992-11-01), None
Gainey Trevor C.
Miaoulis Niko
Clark Sheila V.
LSI Logic Corporation
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