Method of fabricating self-aligned multilevel mask ROM

Details Method of fabricating self-aligned multilevel mask ROM Method of fabricating self-aligned multilevel mask ROM

2001-02-28

2001-11-20

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S278000

Reexamination Certificate

active

06319781

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method of fabricating a mask read only memory (ROM), and more particularly to a method of fabricating a high density mask ROM with multilevel cell transistor by using self-aligned code implantation.
BACKGROUND OF THE INVENTION
Mask ROM is generally made from a number of cell transistors, each serving as a memory unit. When programming is required, ions are implanted into the channel region of selected memory cells so that threshold voltage of these cells is modified. The ‘on’ or ‘off’ state of each memory cell is thus set. In general, a memory cell is created whenever a word line (WL) crosses over a bit line (BL). The memory cell is formed in the word line covered area between two neighboring bit lines. Each memory cell is capable of storing a binary bit of data, either in a logic state of ‘0’ or ‘1’ depending on whether the channel region of the memory cell is implanted or not.
However, when the generation of the mask ROM fabrication is migrated into deep-sub-micro semiconductor process, the higher integration of the integrated circuit, the smaller size of the semiconductor device. While ions implanted into the channel region of selected memory cells, location of the implanting region may have misalignment, so that shifts the threshold voltage of transistors. If location of the implanting region is misaligned, may be shifted to the direction of word line or bit line, this will directly cause data storage error of the ROM cell and disturb the neighboring implanting regions to affect operation property of the memory cell, especially in the shift of word line direction. A conventional way to resolve the problem is using a phase-shift mask (PSM) to program the ROM code. However, this will greatly increase manufacture cost and time so that PSM is not economic.
In addition, ions are implanted just only one time in programming two-level mask ROM so that the cell transistor only has two cases, ion implanted or not. This results each cell transistor of the two-level mask ROM is indicated to have binary signal of “1” or “0”. When memory capacity of two-level mask ROM is required larger, a mount of cell transistors in the two-level mask ROM is increased, so that reducing the integration of the two-level mask ROM, and further reducing yield of the cell transistors.
SUMMARY OF THE INVENTION
Therefore, the present invention provides a method of fabricating a self-aligned multilevel mask read only memory (ROM). The method of the present invention can prevent shift of the threshold voltage causing from misalignment of ion implantation. By utilizing the height difference between different gate polysilicon layers and implanting ROM code to enlarge difference of gate threshold voltage, a multilevel mask ROM is therefore formed to times the memory capacity.
The present invention provides a method of fabricating a mask read only memory (ROM), comprising: forming a gate oxide layer and a polysilicon layer in sequence on a substrate; defining the polysilicon layer; performing a doping process to form a buried bit line in the substrate by using the polysilicon layer as a mask; defining the polysilicon layer to form a plurality of gate layers; forming a plurality of gate spacers around and on the sidewall of the gate layers; forming a silicon oxide layer over the substrate; removing portion of the silicon oxide layer until exposing the top of the polysilicon layer; forming a first patterned photoresist layer on the substrate to cover parts of the polysilicon layer; removing portion the exposed polysilicon layer by using the first patterned photoresist layer as a mask; performing a first ion implantation process to from a first doped region in the substrate under the exposed polysilicon layer by using the first patterned photresist layer as a mask; removing the first patterned photoresist layer; forming a second patterned photoresist layer on the substrate to cover parts of the polysilicon layer; removing portion of the exposed polysilicon layer by using the second patterned photoresist layer as a mask; performing a second ion implantation process to form a second doped region in the substrate under the exposed polysilicon layer by using the second patterned photoresist layer as a mask; removing the second patterned photoresist layer; and forming a conductive layer on the substrate to electrically connect to the exposed polysilicon layer.


REFERENCES:
patent: 5670402 (1997-09-01), Sogawa et al.
patent: 5712203 (1998-01-01), Hsu
patent: 5946558 (1999-08-01), Hsu
patent: 6037227 (2000-03-01), Hong
patent: 6146949 (2000-11-01), Wu

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