Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-12-03
2001-11-20
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S731000
Reexamination Certificate
active
06321355
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit in which a circuit for testing an LSI is incorporated.
Boundary-scan architecture has been disclosed by IEEE Std 1149.1a-1993, pp. A8-A12, JP-A-4-105077, JP-A-4-20879 and JP-A-7-151829.
The boundary scan is a system for testing the mounting condition (or the short-circuiting and disconnection) of wiring of an LSI mounted on a board or package. In order to realize this testing, a boundary scan circuit connected to a signal input/output pin of the LSI is incorporated in the LSI.
The boundary scan circuit for testing has the following problem. Namely, notwithstanding that the boundary scan circuit does not contribute to the essential specification of the LSI, the circuit occupies a large area of the LSI chip and hence a so-called overhead becomes large. Therefore, a chip portion capable of being used for the realization of the essential operation specification is oppressed or the area of the chip is increased.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a boundary-scan circuit with which an overhead for the area of an LSI is reduced by the combined use of an up dating register which forms a boundary-scan register and a flip-flop circuit which holds data in a user's logic.
Another object of the present invention is to provide an LSI circuit in which the number of gate circuit stages for LSI test mode interposed in a path between an input pin to an LSI chip and a user's logic and causing a signal delay is reduced.
To that end, one aspect of the present invention provides an LSI having a logic circuit and a test circuit, comprising a first register connected between an LSI input/output pin and the logic circuit, the first register having a first input terminal inputted with a signal to be outputted from the first register in accordance with a system clock signal and a second input terminal, a second register having a first input terminal inputted with an output of the first register and a second input terminal inputted with scan-in data, an output of the second register being connected to the second input terminal of the first register, a selector circuit connected to one input terminal of the first input terminal of the second register and the second terminal of the first register for selecting one of a signal relating to scan-out data and an output signal of the other register so that the selected signal is inputted to the one input terminal, and a third register for receiving an output of the second register and providing the received output as scan-out data in accordance with another clock signal.
An output of the third register is successively provided to another LSI input/output pin.
The selector circuit includes a logic gate circuit inputted with a signal indicative of an LSI test mode and the output signal of the other register.
According to another aspect of the present invention, there is provided a boundary scan circuit which is disposed between an LSI input pin and a user's logic in an LSI circuit having a JTAG circuit incorporated therein and includes a boundary scan register composed of a master register for shifting, a slave register for shifting, and a register for updating provided at a stage in rear of the master shifting register,
wherein one terminal pair of a flip-flop for user's logic disposed immediately after the LSI input pin and having two terminal pairs each including an input signal terminal and a clock signal input terminal is used as a data input terminal for user's logic and a terminal for system clock and the other terminal pair is used as a scan data input terminal and a terminal for scan clock so that the flip-flop for user's logic is used as the updating register,
wherein the scan data input terminal of the flip-flop for user's logic is inputted with boundary scan data which is to be transferred from the master shifting register to the slave shifting register at the time of boundary scan, and
wherein a control circuit for selecting, by an LSI scan mode signal at the time of LSI scan mode, LSI scan-in data inputted from the LSI input pin to the data input terminal for user's logic of the flip-flop for user's logic and outputted from an output terminal of the flip-flop is provided and an output of the control circuit is inputted to the master shifting register.
It may be constructed that at the time of LSI scan mode, the LSI scan-in data is transferred in such a clock two-stage transfer manner that the LSI scan-in data from the LSI input pin is inputted to the data input terminal for user's logic of the flip-flop for user's logic in accordance with a system clock signal and an output of the flip-flop for user's logic is thereafter taken into the master shifting register in accordance with a clock signal for taking the output of the flip-flop into the master shifting register, and an output of the master shifting register is scanned out through the slave shifting register. With this construction in which the LSI scan-in data is scanned out through the shifting registers of the boundary scan circuit, the flip-flop for user's logic used as the updating register for updating is enabled to make scan-in/out at the time of LSI circuit test such as INTEST, RUNBIST or the like which is the JTAG standard. Further, the diagnosis of the user's logic side is enabled.
According to a further aspect of the present invention, there is a boundary scan circuit which is disposed between a user's logic and an LSI output pin in an LSI circuit having a JTAG circuit incorporated therein and includes a boundary scan register composed of a master register for shifting, a slave register for shifting, and a register for updating provided at a stage in rear of the master shifting register,
wherein one terminal pair of a flip-flop for user's logic disposed immediately before the LSI output pin and having two terminal pairs each including an input signal terminal and a clock signal input terminal is used as a data input terminal for user's logic and a terminal for system clock and the other terminal pair is used as a scan data input terminal and a terminal for scan clock so that the flip-flop for user's logic is used as the updating register, and
wherein a control circuit for selecting an output of the master shifting register at the time of boundary scan and LSI scan-out data at the time of LSI scan-out in accordance with an LSI scan mode signal is provided and an output of the control circuit is inputted to the scan data input terminal of the flip-flop for user's logic.
REFERENCES:
patent: 5390190 (1995-02-01), Nanda et al.
patent: 5831993 (1998-11-01), Graef
patent: 5896396 (1999-04-01), Sanghani et al.
patent: 5920575 (1999-06-01), Gregor et al.
patent: 4-20879 (1992-01-01), None
patent: 4-105077 (1992-04-01), None
patent: 7-151829 (1995-06-01), None
Izaki Kouji
Takahashi Tetsuya
Yamagata Ryo
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Tu Christine T.
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