Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2000-08-30
2001-10-16
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S185090
Reexamination Certificate
active
06304504
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to semiconductor memory devices, and in particular, the present invention relates to testing and stressing semiconductor memory devices for bitline-to-bitline shorts.
BACKGROUND OF THE INVENTION
Electronic information handling or computer systems, whether large machines, microcomputers or small and simple digital processing devices, require memory for storing data and program instructions. Various memory systems have been developed over the years to address the evolving needs of information handling systems. One such memory system includes semiconductor memory devices.
Semiconductor memory devices are rapidly-accessible memory devices. In a semiconductor memory device, the time required for storing and retrieving information generally is independent of the physical location of the information within the memory device. Semiconductor memory devices typically store information in a large array of cells. A group of cells are electrically connected together by a bitline, or data line. An electrical signal is used to program a cell or cells. The electrical signal on the data line is controlled by a driver circuit. Accordingly, a semiconductor memory device may include several groups of cells, each coupled together with a bitline operated by a driver circuit.
Computer, communication and industrial applications are driving the demand for memory devices in a variety of electronic systems. One important form of semiconductor memory device includes a non-volatile memory made up of floating-gate memory cells called flash memory. Computer applications use flash memory to store BIOS firmware. Peripheral devices such as printers store fonts and forms on flash memory. Digital cellular and wireless applications consume large quantities of flash memory and are continually pushing for lower voltages and higher densities. Portable applications such as digital cameras, audio recorders, personal digital assistants (PDAs) and test equipment use flash memory cards as the medium to store data, send and receive wireless faxes, and store digital audio clips and digital images. Each of these applications requires large amounts of highly reliable memory.
Prior to shipping, a manufacturer may test its semiconductor memory devices as part of a quality program to improve end-use reliability. One of the tests performed includes a bitline stress test. Generally, the bitline stress test is used to stress the materials of which the memory cells are made. In the bitline stress test, a higher voltage than usual is applied to all of the cells in a group. During such a test, a voltage is applied across the memory cell terminals while the memory cell is in a non-conductive mode. A leakage current may indicate a short within the memory device. Using a voltage for the bitline stress test that is higher than operating voltages may also simulate extended aging on the memory device. Thus, the higher-than-normal voltage may identify or even induce a short that might not otherwise affect device performance until after extended field use of the memory device. This short may be highly resistive and not affect the operation of the memory device. It may, however, degrade the operation over time. While the global stress test described above may identify a short within a memory device, it is generally incapable of identifying bitline-to-bitline defects with particularity.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternate bitline stress test methods for semiconductor memory devices and circuitry to support such test methods.
SUMMARY OF THE INVENTION
The above-mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
Memory devices having architectures permitting the application of a voltage differential across alternate bitlines are described herein. Such memory device architectures facilitate identifying and locating shorts within the memory device. By applying the voltage differential across alternate bitlines, measuring the current leakage induced by the voltage differential, and comparing the current leakage to a predetermined threshold leakage value, shorts within the memory device are identified. Repetition of the procedure at various levels, such as the device level, block level, packet level or bitline level, can be used to not only identify the existence of a short, but to also locate the short with desired specificity.
For one embodiment, the invention provides a memory array. The memory array includes memory cells coupled to bitlines. The memory array further includes first selective coupling devices coupled between a first plurality of bitlines and a first variable potential node and second selective coupling devices coupled between a second plurality of bitlines and a second variable potential node. Each bitline of the first plurality of bitlines is adjacent at least one bitline of the second plurality of bitlines.
For another embodiment, the invention provides a memory array. The memory array includes memory cells coupled to bitlines. The memory array further includes first selective coupling devices coupled between a first plurality of bitlines and a first level shifter for selectively providing at least a first potential and a second potential to the first plurality of bitlines. The memory array still further includes second selective coupling devices coupled between a second plurality of bitlines and a second level shifter for selectively providing at least the first potential and the second potential to the second plurality of bitlines.
For yet another embodiment, the invention provides a memory array. The memory array includes memory cells coupled to bitlines and a bitline discharging circuit coupled to the bitlines. The bitline discharging circuit includes first selective coupling devices coupled between a first plurality of bitlines and a first variable potential node. The bitline discharging circuit further includes second selective coupling devices coupled between a second plurality of bitlines and a second variable potential node.
For a further embodiment, the invention provides a memory array. The memory array includes memory cells coupled to bitlines, wherein the bitlines include a first plurality of even bitlines and a second plurality of odd bitlines. The memory array further includes a first level shifter for providing one of at least two first potential states as a first bitline potential, a second level shifter for providing one of the at least two first potential states as a second bitline potential, a third level shifter for providing one of at least two second potential states as a first control signal, and a fourth level shifter for providing one of the at least two second potential states as a second control signal. The memory array still further includes first field-effect transistors each having a first source/drain region coupled to one of the first plurality of even bitlines, a second source/drain region coupled to the first level shifter for receiving the first bitline potential, and a gate coupled to the third level shifter for receiving the first control signal. The memory array still further includes second field-effect transistors each having a first source/drain region coupled to one of the second plurality of odd bitlines, a second source/drain region coupled to the second level shifter for receiving the second bitline potential, and a gate coupled to the fourth level shifter for receiving the second control signal.
For a still further embodiment, the invention provides a method of testing a memory device. The method includes applying a first potential to a first plurality of bitlines of the memory device and applying a second potential to a second plurality of bitlines of the memory device. Each bitline of the first plurality of bit
Chevallier Christophe J.
Louie Benjamin
Fogg Slifer & Polglaze, P.A.
Leffert Thomas W.
Micro)n Technology, Inc.
Nguyen Tan T.
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