Trench storage dynamic random access memory cell with...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S301000, C438S242000

Reexamination Certificate

active

06184549

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to integrated circuit dynamic random access memories, and more particularly to trench capacitor construction.
2. Background Description
As dynamic random access memory (DRAM) cells are scaled to meet chip-size requirements for future generations, the channel length of transfer devices on the surface of the silicon substrate can no longer be scaled without degrading subthreshold leakage requirements (or retention time requirements). Process steps become complex and incompatible with standard DRAM processes, when vertical transfer devices in the DRAM cell are employed to decouple the channel length from layout ground rules.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a vertical transfer device which is built on top of a deep trench storage node and is compatible with contemporary DRAM process steps.
By integrating a robust transfer device in a Dynamic Random Access Memory (DRAM) cell having a shallow trench isolation (STI) region constructed between adjacent trench capacitor cells, having the transfer device region bound by shallow trench isolation oxide, the device channel length requirement is independent of the cell size. As an example, the inventive process may use a 256 Mb DRAM cell with 0.25 &mgr;m ground rules. The process is also applicable to other ground rules. The structures formed in the inventive process are most useful as ground rules are reduced and DRAM density is increased. The horizontal layout allows the product to be scaled with changing ground rules.


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