Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-01-08
2001-10-23
Lebentritt, Michael (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S303000, C438S305000, C438S586000, C438S689000
Reexamination Certificate
active
06306715
ABSTRACT:
BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the fabrication of a MOS transistors where the gate is etched to reduce the channel length.
2) Description of the Prior Art
As semiconductor devices are scaled down, there is a need to more accurately control the gate width and channel width. There is a need to find a process that allows channel regions and gate widths to more accurately controlled. There is also a need to find a process that allows channel regions and gate widths to more reduced below the lithographic limits.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,334,545(Caviglia) shows method for forming a gate and etching the poly bottom gate material.
U.S. Pat. No. 4,528,066(Merkling, Jr., et al.) shows process to eliminate undercutting under a gate.
U.S. Pat. No. 6,037,630(Igarashi et al.) shows a gate process.
U.S. Pat. No. 5,786,253(Hsu) shows a ROM cell with conductive lines.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating a MOS transistor that has a process that allows channel regions and gate widths to more accurately controlled.
It is an object of the present invention to provide a method for fabricating a MOS transistor that allows channel regions and gate widths to more reduced below the lithographic limits.
To accomplish the above objectives, the present invention provides a method of manufacturing a MOS transistor. The invention describes two embodiments of a method for forming a two layer gate, and etching the bottom gate material to undercut the top gate portion. The first embodiment uses a spacer. The second embodiment uses only a selective etch process, and no spacers.
The first embodiment of the invention is described as follows. A gate dielectric layer is formed over a substrate. Next, a first gate layer is formed over the gate dielectric layer. Subsequently, a second gate layer (blanket deposition) is formed over the first gate layer. We pattern the second gate layer to form a second gate portion over the first gate layer. Spacers are formed on the sidewalls of the second gate portion. In a critical step, we isotropically etch the first gate layer to undercut the second gate portion to form a first gate portion so that the first gate portion has a width less than the second gate portion. The first gate portion is narrower than the second gate portion. In a critical step, we remove the spacers. Next, we form lightly doped drains adjacent to the first gate portion and under the second gate portion. The lightly doped drain is formed using an angled ion implant so that the lightly doped drain is implanted under the second gate portion and the first gate portion. We form sidewall spacers on the sidewalls of the first and second gate portions. Next, we form source/drain regions adjacent to the sidewall spacers.
The second embodiment is described as follows. A gate dielectric layer is formed over a substrate. A first gate layer is formed over the gate dielectric layer. We form a second gate layer over the first gate layer. The second gate layer is patterned to form a second gate portion over the first gate layer. We isotropically etch the first gate layer to undercut the second gate portion to form a first gate portion so that the first gate portion has a width less than the second gate portion. The first gate portion is narrower than the second gate portion. We form a lightly doped drain adjacent to the first gate portion and under the second gate portion. A lightly doped drain is formed preferably using an angled ion implant so that the lightly doped drain is implanted under the second gate portion and the first gate portion. Sidewall spacers are formed on the sidewalls of the first and second gate portions. Source/drain regions are formed adjacent to the sidewall spacers.
The invention allows us to control the channel length by the thickness of the first gate layer and the amount of undercut from the isotropic etch of the first gate layer.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.
REFERENCES:
patent: 4528066 (1985-07-01), Merkling, Jr. et al.
patent: 5210435 (1993-05-01), Roth et al.
patent: 5334545 (1994-08-01), Caviglia
patent: 5416033 (1995-05-01), Lee et al.
patent: 5427971 (1995-06-01), Lee et al.
patent: 5620912 (1997-04-01), Hwang et al.
patent: 5650343 (1997-07-01), Luning et al.
patent: 5716861 (1998-02-01), Moslehi
patent: 5786253 (1998-07-01), Hsu
patent: 5840611 (1998-11-01), Lee et al.
patent: 5989965 (1999-11-01), Maa et al.
patent: 6037630 (2000-03-01), Igarashi et al.
patent: 6069387 (2000-05-01), Gardner
Chan Lap
Lee James Yong Meng
Leung Ying Keung
Pan Yang
Pradeep Yelehanka Ramachandramurthy
Chartered Semiconductor Manufacturing Ltd.
Lebentritt Michael
Pike Rosemary L. S.
Saile George O.
Stoffel William J.
LandOfFree
Method to form smaller channel with CMOS device by isotropic... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method to form smaller channel with CMOS device by isotropic..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method to form smaller channel with CMOS device by isotropic... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2611366