Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2000-11-14
2001-11-20
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S109000, C438S113000
Reexamination Certificate
active
06319750
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor packaging technology, and more particularly, to a layout method for a semiconductor package substrate with a plating bus, such as a TFBGA (Thin & Fine Ball Grid Array) substrate, which can help allow each singulated package unit from the TFBGA substrate to be substantially free of trace short-circuits due to misaligned cutting during singulation process.
2. Description of Related Art
BGA (Ball Grid Array) is an advanced type of semiconductor packaging technology which is characterized in the use of a substrate whose front surface is used for the mounting of a semiconductor chip thereon, and whose back surface is used for the mounting of a grid array of solder balls to allow the entire package body to be mechanically bonded and electrically coupled to an external printed circuit board (PCB). This structure allows the BGA package to be made very compact in size.
TFBGA (Thin & Fine Ball Grid Array) is a downsized type of BGA technology that provides semiconductor packages in very small sizes, which are customarily fabricated in batch from a single large-size chip carrier, such as a substrate. The large-size TFBGA substrate is predefined with a matrix of package sites, and an individual TFBGA package unit can be obtained by cutting apart each package site from the TFBGA substrate through singulation process.
In layout design, a TFBGA substrate is typically predefined with a great number of bond pads, electrically-conductive traces, and solder-ball pads, which are separately located at different locations all over the package sites. During the TFBGA fabrication, it is required to plate an electrically-conductive material, such as the alloy of nickel and gold (Mi—Au), onto these traces and pads to make them highly conductive to electricity. To facilitate the plating process, these traces and pads are all connected in layout design to, a provisional plating bus, which is used to conduct electricity to al the traces and pads during plating process, and which can be cut away in the final singulation process.
A conventional layout method for TFBGA substrate with plating bus is depicted in the following with reference to
FIGS. 1A-1C
.
FIG. 1A
shows a schematic plan view of the front surface of a TFBGA substrate
100
utilizing a conventional layout method (note that
FIG. 1A
is simplified to show only a small number of electrically-conductive trades and via lands for demonstrative purpose; the actual layout may be much more complex).
As shown, this TFBGA substrate
100
is predefined into a plurality of package sites (only two are shown in
FIG. 1A
, respectively designated by the reference numerals
110
a,
110
b
) which are delimited by a plurality of crosswise and lengthwise singulation lines SL
X
, SL
Y
. In the final singulation process, the respective package sites
110
a,
110
b
can be cut apart into individual package units along these predefined singulation lines SL
X
, SL
Y
.
These package sites
110
a,
110
b
are predefined with the sane circuit layout, wherein the package site
110
a
is predefined with at least one die-mounting area
111
a
which is associated with a plurality of crosswise-extending electrically-conductive traces
112
a
and two rows of via lands
113
a
located on both sides of the die-mounting area
111
a
and alongside the nearby lengthwise singulation lines SL
Y
, and similarly, the neighboring package site
110
b
is predefined with at least one die-mounting area
111
b
which is associated with a plurality of crosswise-extending electrically-conductive traces
112
b
and two rows of via lands
113
b
located on both sides of the die-mounting area
111
b
and alongside the nearby lengthwise singulation lines SL
Y
.
The via lands
113
a,
113
b
define the locations where electrically-conductive vias (not shown) are formed to interconnect the electrically-conductive traces
112
a,
112
b
on the front surface of the TFBGA substrate
100
with the solder-ball pads (not shown) on the back surface of the same. Since the fabrication of these vias (not shown) and solder-ball pads (not shown) is not within the spirit and scope of the invention, description thereof will not be further detailed.
During the TFBGA fabrication, it is required to perform plating on the bonding finger area
111
a,
111
b
electrically-conductive traces
112
a,
112
b
on the front surface and the solder-ball pads (not shown) on the back surface. To facilitate the plating process, the via lands
113
a,
113
b
are all connected to a common plating bus
120
, so that the electricity used during the plating process can be applied to the plating bus
120
and then concurrently distributed by the plating bus
120
by way of the via lands
113
a,
113
b
and the electrically-conductive traces
112
a,
112
b
to the bonding finger area
111
a,
111
b
on the front surface and the solder-ball pads (not shown) on the back surface of the TFBGA substrate
100
.
In layout design, the plating bus
120
is formed in a grid shape and laid directly over the crosswise and lengthwise singulation lines SL
X
, SL
Y
, so that in the final singulation process, the plating bus
120
can be entirely cut away.
One drawback to the forgoing layout method, however, is that, since the TFBGA substrate
100
is typically very small in size, where the plating bus
120
is typically from 0.05 mm to 0.1 mm (millimeter) in width and the cutting blade (not shown) used in the singulation process is typically 0.3 mm in width, the alignment of the cutting blade (not shown) to the singulation lines SL
X
, SL
Y
should be highly precisely controlled; otherwise, in the case that the misalignment exceeds 0.115 m, it would cause the problem of trace short-circuits.
As shown in
FIG. 1B
, when the cutting blade's position (designated by CB) is misaligned to the singulation line SL
Y
, then it would be likely to leave an edge part of the plating bus
120
beyond the cutting range.
As shown in
FIG. 1C
, in the case of an overly misaligned cutting during singulation process, a small edge part of the original plating bus (designated here by the reference numeral
121
) might be left over the edge of the singulated package site
110
a,
which would cause the electrically-conductive traces
112
a
on the package site
110
a
to be short-circuited to each other. When this is the case, the singulated TFBGA package unit would be regarded as defective.
FIG. 2
shows a solution to the foregoing problem of trace short-circuits due to misaligned cutting during singulation process.
As shown, this improved layout method is utilized on a TFBGA substrate
200
predefined into a plurality of package sites (only two are shown in
FIG. 2
, respectively designated by the reference numerals
210
a,
210
b
which are delimited by a plurality of crosswise and lengthwise singulation lines SL
X
, SL
Y
.
The package site
210
a
is predefined with at least one die-mounting area
211
a
which is associated with a plurality of crosswise-extending electrically-conductive traces
212
a
and two rows of via lands
213
a
located on both sides of the die-mounting area
211
a
and alongside the nearby lengthwise singulation lines SL
Y
. In largely the same manner, the neighboring package site
210
b
is also predefined with at least one die-mounting area
211
b
which is associated with a plurality of electrically-conductive traces
212
b
and two rows of via lands
213
b
located on both sides of the die-mounting area
211
b
and alongside the nearby lengthwise singulation lines SL
Y
. However, in order to facilitate this improved layout method, it is to be noted that the right row of via lands
213
a
within the first package site
210
a
are unaligned in line to the left row of via lands
213
b
within the second package sites
210
b.
This improved layout method is characterized in that all of the via lands
213
a,
213
b
that are laid on both sides of each lengthwise singulation line ST
Y
are all connected to a zigzag plating bus
220
extending in a
Ho Tzong-Da
Huang Chien-Ping
Corless Peter F.
Edwards & Angell LLP
Le Thao P
Nelms David
Siliconware Precision Industries Co., LTD.
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