Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Die bond
Reexamination Certificate
1999-08-06
2001-11-20
Clark, Jhihan B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Die bond
C257S678000, C257S693000, C257S784000, C257S701000
Reexamination Certificate
active
06320267
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device and a manufacturing method thereof and more particularly to a semiconductor device having a semiconductor chip bonded on a radiator plate with interposition of a bonding layer.
2. Description of the Related Art
It has been required that consumer appliances are made compact and the requirement has called for one chip structuring of a semiconductor device or high density mounting of a semiconductor device, and thus area array packages such as ball grid array, in which external connecting terminals are arranged in the form of two-dimensional area (referred to simply as “BGA” hereinafter), and land grid array (referred to simply as “LGA” hereinafter) have been proposed and practically used to satisfy the requirement for multi-pin semiconductor.
As a related area package, tape BGA (Tape-BFA, referred to simply as “T-BGA” hereinafter), in which TAB (Tape Automated Bonding) is used as interconnection technique, is described referring to FIG.
2
.
For example, a semiconductor chip
44
is bonded on a radiator plate
40
consisting of copper material with interposition of a paste bonding layer
42
. Many electrode pads
46
are formed on the surface of the semiconductor chip
44
.
On the circumference of the radiator plate
40
surrounding the semiconductor chip
44
, a stiffener
50
is bonded with interposition of a bonding layer
48
. On the stiffener
50
, many external connecting terminals
54
having a ball-shaped end respectively are arranged dispersedly in the form of array.
These many external connecting terminals
54
are connected to the electrode pads on the semiconductor chip
44
with interposition of respective inner leads
56
. These many external connecting terminals
54
are covered with an insulating film
58
excepting the ball-shaped ends and insulated stably each other. As described herein above, the external connecting terminals
54
, inner leads
56
, and insulating film
58
constitute a wiring pattern
60
for connecting the electrode pads of the semiconductor chip
44
to the external.
The semiconductor chip
44
bonded on the radiator plate
40
with interposition of the paste bonding layer
42
and the inner leads
56
connected to the electrode pads
46
are covered with sealing resin
62
, this is so-called resin sealing.
As described herein above, in the T-BGA, because many external connecting terminals
54
are arranged dispersedly in the form of array on the stiffener
50
surrounding the semiconductor chip
44
, the package size of a T-BGA is made small even if the pitch of the external connecting terminals
54
of the semiconductor device having many pins is relatively large, for example, 1.0 mm or 0.27 mm, therefore this structure is effective for high density mounting.
Further, the semiconductor chip
44
is bonded directly on the radiator plate
40
with interposition of the paste bonding layer
42
, and therefore heat generated from the semiconductor element during operation is easily dissipated, thus this structure is also effective for low heat resistance packaging.
However, in the above-mentioned T-BGA, the thermal expansion coefficient of the semiconductor chip
44
is approximately 3 ppm/° C. and the thermal expansion coefficient of the radiator plate
40
consisting of copper material is approximately 17 ppm/° C., the large difference in the thermal expansion coefficient between both components causes the stress concentration on the paste bonding layer
42
between the semiconductor chip
44
and the radiator plate
40
, for example, when the semiconductor device is subjected to a thermal cycle test (referred to simply as T/C test hereinafter), in which the temperature of the T-BGA is varied cyclically, the bonding strength of the paste bonding layer
42
is decreased to cause cracking or separation occasionally at the end.
As described herein above, though the semiconductor device is excellent in heat dissipation initially as it is fabricated, after T/C test, the bonding strength of the paste bonding layer
42
which has been subjected to stress concentration is decreased, and good contact between the semiconductor chip
44
and the radiator plate
40
is deteriorated to result in significantly reduced heat dissipation, and thus the reliability in endurance becomes poor disadvantageously.
Not only T-BGA but also semiconductors of other types as long as a bonding layer is provided between a semiconductor chip and a radiator plate or a die pad consisting of copper material are involved generally in the problem.
SUMMARY OF THE INVENTION
The present invention has been accomplished to solve the above-mentioned problem, and the object of the present invention is to provide a semiconductor device having a semiconductor chip bonded on a radiator plate with interposition of a bonding layer in which stress concentration caused in the bonding layer is relaxed to maintain the heat dissipation performance and which is excellent in reliability in endurance and a method for manufacturing thereof.
The inventors of the present invention examined the reduction of stress concentration caused in a bonding layer between bonded bodies formed of different materials due to the difference in thermal expansion coefficient between these materials to solve the above-mentioned problem.
In general, sufficiently thick thickness of a bonding layer is required to relax stress concentration on the bonding layer to be provided between a semiconductor chip and a radiator plate which have the different thermal expansion coefficient each other. However, it is difficult to form an even bonding layer having a sufficient thickness with a single layer of a related paste-based bonding layer, and a bonding layer having the sufficiently thick thickness can not be realized.
To secure an even bonding layer having a thickness sufficient for the bonding layer to relax stress concentration caused on the bonding layer, the inventors tried to use a thermoplastic film bonding layer instead of paste-based bonding layer. In this case, though it was easily achieved to form an even bonding layer having a sufficient and necessary thickness, the bonding layer was involved in the problem of blistering in at least any one of interfaces between a semiconductor chip and the thermoplastic film bonding layer or a radiator plate and the thermoplastic film bonding layer when the thermoplastic film bonding layer placed between a semiconductor chip of a hard material and a radiator plate of a hard material was press-bonded together. In detail, though no blistering was not caused when a thermoplastic film bonding layer was bonded on a semiconductor chip or a radiator plate, however, it was very difficult to prevent blistering when a radiator plate or a semiconductor chip was press-bonded on the thermoplastic film bonding layer bonded on the semiconductor chip or the radiator plate. The existence of the blister resulted in reduced bonding strength and reduced heat dissipation performance of the bonding layer.
Experiments were repeated to find a bonding layer for forming an even bonding layer having a necessary and sufficient thickness to relax stress concentration by a method in which blistering was prevented so as not to cause reduction of bonding strength and reduction of heat dissipation performance. As the result, the semiconductor device and the method for manufacturing thereof in accordance with the present invention has been accomplished.
In detail, a semiconductor device in accordance with one aspect of the present invention is a semiconductor device having a semiconductor chip bonded on a radiator plate with interposition of a bonding layer, wherein the bonding layer comprises a laminated structure including a thermoplastic film bonding layer and a paste-based bonding layer.
In the semiconductor device in accordance with one aspect of the present invention, because the laminated structure including the thermoplastic film bonding layer and the paste-based bonding layer is employed as the bonding lay
Clark Jhihan B
Sonnenschein Nath & Rosenthal
Sony Corporation
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