Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-09-29
2001-12-04
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S425000, C438S978000, C257S374000, C257S510000
Reexamination Certificate
active
06326255
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device having a highly reliable groove isolation structure and a semiconductor device manufactured by the method.
An SGI (Shallow Groove Isolation) structure is one of the typical structures for electrically insulating adjacent elements such as transistors on a semiconductor substrate. This SGI structure is formed as follows At first, a pad oxide film and an oxidation inhibition film are formed ona silicon substrate. Then, a shallow groove is also formed on an insulating portion of the silicon substrate. Next, the oxide film is coated on the shallow groove by means of thermal oxidation and then an insulating film is coated on the oxide film.
The SGI structure is suitable for the device of 0.25 &mgr;m process or smaller, because it has a higher precision in working dimension than the conventionally-used LOCOS structure.
However, this SGI structure has a problem that a silicon shape on an upper end of the groove may become acute in the thermal oxidation If the acute portion is left on the surface of the substrate, for example, as published by A. Bryant et al. in “Technical Digest of IEDM '94, pages 671 to 674, an electric field is concentrated on this acute portion while the circuit is in operation, so that the withstand characteristics of the transistors or the capacitors composing the circuit may be degraded.
It is experientially known that the degrade of the withstand characteristics takes place in the case that the curvature radius of the substrate around the upper end of the groove is 3 nm or lower even if the angle of the substrate around the upper end of the groove is 90 degrees or more. In order to solve these problems, as indicated in JP-A-2-260660, it is possible to form the pad oxide film on a lower portion so as to recede from the upper end of the groove by 0.1 &mgr;m and perform the oxidation with a gas containing vapor at a temperature of around 1000° C., for forming a curvature on the upper end of the groove.
As indicated in JP-A-6-21214, after forming a groove on the silicon substrate, amorphous silicon or epitaxial silicon is deposited to have a thickness of 5 nm or more. Then, the coat is oxidized at a temperature of 1100 to 1150° C. and in the atmosphere of oxygen whose pressure is lowered by 20%. This is the indicated method of forming a curvature on the upper end of the groove.
In this method of depositing amorphous silicon, on the upper end of the groove, the amorphous silicon film is made thinner than the tabular portion of the substrate. Hence, the oxidation in this state preferentially makes the corner oxidized, so that the corner of the silicon substrate is made round.
Moreover, if the method of depositing the epitaxial silicon film is executed after forming the groove, as a result, the corner is chamfered so that the shape after oxidation is made round.
SUMMARY OF THE INVENTION
However, if the semiconductor is produced by the conventional method disclosed in JP-A-2-260660, since the receded amount of the pad oxide film is 0.1 &mgr;m, stepped portion may be generated around the upper end of the groove on the silicon substrate. Further, if the oxidation is large in this method, the curvature is formed when the stepped portion is formed, while if the oxidation is small, especially, about 10 nm, the portion around the upper end of the groove may be acute.
When forming a gate oxide film on such a stepped portion and an acute portion, the thickness of the oxide film is made uneven, on which film electric weak spots are formed. Moreover, since it is more likely that the stress is concentrated on these portions, the electric reliability of the transistors on the stepped portions may be made lower.
According to the method of depositing amorphous silicon after forming the groove as disclosed in the prior art of JP-A-6-21214, the amorphous silicon film may have the same thickness as the tabular portion even at the corner of the upper end of the groove, which may often make it difficult to round the corner.
Further, in the method of growing the epitaxial silicon film, the shape of the corner may not be chambered in the actual layout.
It is an object of the present invention to provide a method of manufacturing a semiconductor device and a semiconductor device manufactured by the method which make it possible to reliably form a curvature on the upper end of the groove without forming the foregoing stepped portions and even in the case of the small oxidation (about 10 nm).
The object is achieved by the following method:
(A) A method of manufacturing a semiconductor device includes the steps of (1) forming a pad oxide film of 5 nm or more on a circuit forming surface of a semicnductor substrate; (2) forming an oxidation inhibition film on the pad oxide film; (3) forming a groove of a given depth with the oxidation inhibition film as a mask; (4) receding the pad oxide film; (5) oxidizing a groove portion formed on the semiconductor substrate in the range of 0<C≦0.88t-924 in which the oxidation atmosphere is in the dry oxidizing state (H2/O2≈0) and the oxygen partial pressure ratio, that is, the partial pressure of oxygen is C %, and the oxidation temperature is t (° C.); (6) burying an insulating film in the oxidized groove; (7) removing the buried insulating film formed on the oxidation inhibition film; (8) removing the oxidation inhibition film formed on the circuit forming surface of the semiconductor substrate; and (9) removing the pad oxide film formed on the circuit forming surface of the semiconductor substrate.
(B) Preferably, in the foregoing item (A), at the step (6) of receding the pad oxide film, the pad oxide film is receded from the upper end of the groove of the semiconductor substrate by the range of 10±5 nm.
(C) A semiconductor device is manufactured by the process of forming a pad oxide film of 5 nm or more on a circuit forming surface of a semiconductor substrate; forming an oxidation inhibition film on the pad oxide film; forming a groove of a given depth with the oxidation inhibition film as a mask; receding the pad oxide film; oxidizing a groove portion formed on the semiconductor substrate in the range of 0<C≦0.88t-924 in which the oxidation atmosphere is in the dry oxidizing state (H2/O2≈0) and the oxygen partial pressure ratio, that is, the partial pressure of oxygen is C %, and the oxidation temperature is t (° C.); burying an insulating film in the oxidized groove; removing the buried insulating film formed on the oxidation inhibition film; removing the oxidation inhibition film formed on the circuit forming surface of the semiconductor substrate; and removing the pad oxide film formed on the circuit forming surface of the semiconductor substrate.
(D) Preferably, in the foregoing item (C), the recession of the pad oxide film is defined in the range of 10±5 nm from the upper end of the groove of the semiconductor substrate.
If the groove portion is oxidized in the range of 0<C≦0.88t-924 in which the oxygen partial pressure is C % and the oxidizing temperature is t (° C.), the curvature radius of the corner is 3 nm or more, which does not bring about any defect.
Since the oxygen partial pressure ratio C is 0 or more, no oxidation is done. Hence, the oxidizing temperature is in the range of C≦0.88t-924 to 1050° C. or more.
REFERENCES:
patent: 5863827 (1999-01-01), Joyner
patent: 5956598 (1999-09-01), Huang et al.
patent: 6057241 (2000-05-01), Matsuda et al.
patent: 6090684 (2000-07-01), Ishitsuka et al.
patent: 6909684 (2000-07-01), Ishitsuka et al.
Funabashi Michimasa
Ikeda Shuji
Ishitsuka Norio
Miura Hideo
Suzuki Norio
Antonelli Terry Stout & Kraus LLP
Elms Richard
Hitachi , Ltd.
Pyonin Adam
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