Method of forming self-isolated and self-aligned 4F-square...

Details Method of forming self-isolated and self-aligned 4F-square... Method of forming self-isolated and self-aligned 4F-square...

2000-07-26

2001-11-13

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S247000, C438S249000

Reexamination Certificate

active

06316309

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed to densely packed vertical transistors in a 4F-square memory cell, and methods for making thereof, and more particularly, to memory cells having self aligned sources with deep trench capacitors formed in trenches that separate the vertical transistors.
2. Discussion of the Prior Art
There is much interest to scale down densely packed semiconductor devices on an integrated circuit (IC) chip to reduce size and power consumption of the chip, and allow faster operation. In order to achieve the high packing density necessary for GBit memory applications, it is crucial to shrink the size of an individual memory cell as much as possible.
FIG. 1
shows a top view of a conventional array
10
of conventional erasable programmable read only memory (EPROM) devices
15
, using vertical transistors, such as metal oxide silicon field effect transistors (MOSFETs) with a floating gate layer. The conventional array
10
is described in the following two references. H. Pein and J.D. Plummer, “A 3-D sidewall flash EPROM call and memory array”, Electron Device Letters, Vol. 14 (8) 1993 pp.415-417. H. Pein and J.D. Plummer, “Performance of the 3- D Pencil Flash EPROM Cell and Memory Array”, IEEE Translations on Election Devices, Vol. 42, No. 11, 1995, pp. 1982-1991.
The conventional array
10
has rows of wordlines
20
and columns of bitlines
25
. The size of a cell
27
of the array
10
is 2F by 2F+&Dgr;, leading to a cell area of 4F
2
+2F&Dgr;. F is the minimum line width of the feature size that can be patterned with lithography. 2F is the cell size along the wordline
20
, and 2F+&Dgr; is the cell size along the bitline
25
. Typically, &Dgr; is approximately 0.2-0.5F, resulting in a cell area of approximately 4.4-5.0F
2
area achievable using conventional lithography. The additional length &Dgr; is necessary to separate adjacent wordlines
20
.
FIG. 2
shows a partial perspective view of the array
10
of
FIG. 1
, and
FIG. 3
shows a cross sectional view of the vertical MOSFET
15
along a bitline
25
.
As shown in
FIG. 3
, the MOSFET
15
has an n
+
source
30
formed on a P-doped silicon substrate
35
. The source
30
is formed after etching the substrate
35
to form a vertical pillar
40
, referred to as the body of the MOSFET
15
. The pillar
40
acts as the transistor channel and has dimensions of F by F, as shown in
FIGS. 1 and 3
.
As a result of forming the source
30
after forming the pillars
40
, the source
30
is formed around edges of the pillar
40
and is absent from a region
45
located below the pillar
40
. Thus, the source
30
does not entirely occupy the footprint or lower portion of the pillar
40
. As shown in
FIG. 2
, all the MOSFETs
15
of the array
10
have a common source
30
, including MOSFETs of different bitlines
25
and different wordlines
20
. As shown in
FIGS. 2-3
, the top of each pillar
40
is doped with N-type material to form n
30
drains
50
of the vertical transistors
15
.
tunnel oxide
60
is formed around the pillar
40
and an oxide spacer
65
is formed on the source
30
. Next, a polysilicon floating gate
70
, gate oxide
75
and olysilicon control gate
20
are formed around the tunnel oxide
60
. Note, control gates
20
of individual transistors along the wordline
20
are interconnected to form the wordline
20
.
Because the polysilicon control gate
20
grows uniformly around each vertical MOSFET
15
, the spacing between MOSFETs
15
of adjacent rows is slightly larger than the feature size F, e.g., F+&Dgr;, where a is approximately 0.2F. This separates adjacent wordlines
20
by amount &Dgr;, when polysilicon is grown up to a distance of 0.5F. This 0.5F thick polysilicon layer covers the top and sidewalls of the pillars
40
, as well as the oxide spacer
65
located on the substrate
35
at the base of the pillars
40
.
The 0.5F thick grown polysilicon regions at pillar sidewalls separated by distance F, along each wordline
20
, merge with each other. This forms the wordlines
20
around a row of pillars that are separated by F. However, the 0.5F thick formed polysilicon regions at pillar sidewalls separated by distance F+&Dgr; do not merge. Rather, they remain separated by the distance &Dgr;. At the base of the trenches located between these polysilicon-covered pillar sidewalls that are separated by F+&Dgr;, the oxide spacer
65
is covered with the 0.5F thick polysilicon.
To separate adjacent wordlines
20
, an anisotropic reactive ion etch (RIE) is performed that removes polysilicon for a thickness of 0.5F vertically only. The RIE exposes the top of the pillars
40
, as well as the oxide spacer
65
at the base of the pillars that are separated by F+&Dgr;, leaving a sidewall of polysilicon on the edge of each pillar. The exposed distance of the oxide spacer
65
is &Dgr;. Thus, the &Dgr; separation between adjacent wordlines
20
ensures that control gates
20
of adjacent wordlines are not shorted along the direction of the bitlines
25
.
As shown in
FIGS. 1 and 2
, a first level metal forms bitlines
25
which are orthogonal to the wordlines
20
. The first level metal connects drains
50
of MOSFETs
15
along a common bitline
25
. The area of the cell
27
of
FIG. 2
, is small because the substrate
35
is used as a common source
30
for all the MOSFETs
15
of the array
10
.
FIG. 4
shows a three-dimensional view of another conventional array
90
, which is similar to the conventional array
10
of
FIG. 2
, except for having round pillars
95
instead of square pillars
40
(FIG.
2
). As in the array
10
of
FIG. 2
, the array
90
of
FIG. 4
has a common source
30
.
The memory function of each cell
27
(
FIGS. 1
,
2
)is achieved by charging or discharging the floating gate region
70
. This causes a measurable shift in the threshold voltage of the vertical MOSFET.
However, to make the conventional MOSFETs
15
useful for DRAM applications, the cell must be modified to isolate the source regions
30
between adjacent bitlines
25
. Furthermore, to achieve the packing density necessary for GBit memories, the overall cell area must not be increased by these modifications. The cell area must remain approximately 4F-Square.
One method for achieving source isolation between bitlines
25
is to pattern isolation lines lithographically between the bitlines
25
. Isolation is then achieved by either a local oxidation of silicon (LOCOS), recessed-LOCOS, or conventional shallow trench techniques.
However, such an isolation method requires lithography. Therefore inter-device
20
lines must be increased from F to at least 2F to avoid shorting adjacent control gates, or wordlines
20
along the bitlines. This increases the inter-device spacing along the bitlines
25
from 1.2F to 2F. Thus, the overall cell size increases from 4F
2
+0.4F to at least 6F
2
. Moreover, lithographic misalignment degrades device behavior. Hence, packing density and/or performance is sacrificed in this scheme.
To increase packing density, instead of forming the vertical MOSFET
15
having the pillar
40
, an inverted transistor is formed in a trench etched into the substrate. Such transistor structures are shown in U.S. Pat. Nos. 5,386,132; 5,071,782; 5,146,426 and 4,774,556. The transistors formed in such trenches may be combined with additional planar devices, as discussed in U.S. Pat. Nos. 4,964,080; 5,078,498. Other memory cells have transistors with a floating body, as discussed in U.S. Pat. No. 5,382,540. Another conventional memory cell, disclosed in U.S. Pat. No. 5,017,977, does not have separated buried bitlines between transistors. Such conventional cells fail to achieve maximum packing density due to non-self-aligned isolation techniques, or require complex processing methods for fabrication, e.g., selective epitaxial growth, which methods are not suitable for large-scale production.
Instead of using the vertical devices of the memory cell
27
as an EPROM, the vertical transistor
15
wit

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