Semiconductor memory

Details Semiconductor memory Semiconductor memory

2000-06-28

2001-12-25

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Read/write circuit

Precharge

C365S189011, C365S154000

Reexamination Certificate

active

06333881

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory and, more particularly, to a semiconductor memory having a precharge circuit for write operation, which is effective to shorten recovery time after writing data to an SRAM and to reduce cycle time.
In an SRAM (Static Random Access Memory), recovery time (time required to make a bit line at a high potential to set a potential difference to zero after write operation) is one of the factors which determines the cycle time.
FIG. 2
shows an example of a write circuit and a bit line precharge circuit in a conventional SRAM. Such a conventional technique is disclosed, for example, in “1998 IEEE International Solid-State Circuits Conference, Digest of Technical Papers”, pp. 358-359.
In
FIG. 2
, W
1
and W
2
denote word lines, and BL
1
and BR
1
and BL
2
and BR
2
indicate pairs of bit lines. Memory cells MC
1
to MC
4
are disposed at intersections of the word lines and the pairs of bit lines. WR
1
and WR
2
denote write circuits. The write circuit WR
1
comprises: an NMOS transistor MNL provided between the bit line BL
1
and a power source VSS; an NMOS transistor MNR provided between the bit line BR
1
and the power source VSS; NAND gates NW
1
and NW
2
to which a write control signal WP and data inputs DL
1
and DRI are supplied; and inverters IN
1
and IN
2
, which receive outputs of the NAND gates NW
1
and NW
2
. Output signals NL and NR of the inverters IN
1
and IN
2
are supplied to the gates of the NMOS transistors MNL and MNR, respectively. Although not shown, the write circuit WR
2
is constructed in a manner similar to the write circuit WR
1
.
PR
1
and PR
2
indicate bit line precharge circuits. The bit line precharge circuit PR
1
comprises: a PMOS transistor MP
0
provided between the power source VDD and the bit line BL
1
; a PMOS transistor MP
1
provided between the power source VDD and the bit line BR
1
; and a PMOS transistor MP
2
provided between the bit lines BR
1
and BL
1
. A precharge control signal PU is supplied to the gates of the PMOS transistors MP
0
, MP
1
and MP
2
. Although not shown, the bit line precharge circuit PR
2
is constructed in a manner similar to the bit line precharge circuit PR
1
.
The PMOS transistors will be called precharge PMOS transistors hereinbelow.
FIG. 3
is a diagrammatic sketch of the operations of the conventional technique. The operations of the bit line precharge circuit PR
1
and the write circuit WR
1
, which are connected to the bit lines BL
1
and BR
1
in the conventional circuit, will be described as an example hereinbelow by using
FIGS. 2 and 3
.
In a standby mode, all of the word lines, the precharge control signal PU, and the write control signal WP are at a low potential. The precharge PMOS transistors are conductive, the bit lines BL
1
and BR
1
are at a high potential, and the potential difference (signal amplitude) is zero.
At the time of read operation, first, the precharge control signal PU is set at a high potential and all of the precharge PMOS transistors are made non-conductive. Only one of the word lines corresponding to an address signal is set at a high potential to select a memory cell. In accordance with stored data, a current (cell current) flows to the memory cell from either the bit line BL
1
or BR
1
, so that the potential difference (signal amplitude) occurs between the bit lines. Since the cell current is very small, the signal amplitude of the bit lines at the time of reading operation is small. The signal is generally amplified by a sense amplifier or the like, and the resultant signal is outputted.
At the time of write operation, in a manner similar to the read operation, the precharge control signal PU is set at a high potential to interrupt the precharge PMOS transistors, and only one of the word lines which corresponds to the address signal is set at a high potential. One of the data inputs DL
1
or DR
1
is at a high potential and the other is at a low potential in accordance with the data to be written. When the write signal WP is set at a high potential, one of the output signals NL or NR of the inverters IN
1
and IN
2
comes to have a high potential. Consequently, one of the NMOS transistors MNL or MNR is made conductive, and the potential of one of the bit lines BL
1
or BR
1
is decreased to a low potential, thereby rewriting the data in the memory cell.
After completion of the write and read operations, all of the word lines, write control signal WP, and precharge control signal PU are put back at a low potential, thereby interrupting the memory cell and the write circuit. Further, the precharge PMOS transistors are made conductive, both of the bit lines BL
1
and BR
1
are precharged to a high potential within a certain time, and the signal amplitude becomes zero (the time required by the operation will be called “recovery time” hereinbelow).
When the read operation is performed after the write operation, the minimum cycle time is determined by the recovery time. In this case, when the cycle time is shortened, at a certain point in time, the read operation of the next cycle starts before the potential difference between the pair of bit lines is reduced to zero. In the read operation, data is read by a signal amplitude of the pair of bit lines. Since the signal amplitude is very small, when the potential difference of the bit lines is not set back to zero at the start of the read operation, data cannot be read normally due to the potential difference. There is the possibility that the access time becomes too long and, in the worst case, data is erroneously read.
As described above, the period since the potential difference between the pair of bit lines is set back to zero in the recovery period after completion of the write operation until the start of read operation of the next cycle in the minimum cycle time. The recovery time is therefore one of the factors which determines the cycle time. For the reduction in cycle time by shortening the recovery time, it is sufficient to increase the size of the precharge PMOS transistor. In this case, however, a load capacity to drive the precharge control signal PUS increases. As a result, delay time caused by making the precharge PMOS transistors non-conductive at the start of read operation increases, and a problem of lengthened access time occurs.
SUMMARY OF THE INVENTION
The object of the invention is to provide a semiconductor memory, such as an SRAM having a bit line precharge circuit for shortening the cycle time without increasing access time.
A representative technique disclosed by the invention to achieve the object is discussed below.
According to the invention, there is provided a semiconductor memory comprising: a plurality of word lines; a plurality of bit lines; memory cells disposed at intersections of the word lines and the bit lines; a write circuit for rewriting data in a memory cell by setting the bit line at a low potential; and a first precharge circuit for putting the bit line back at a high potential after completion of at least a read operation, wherein a second precharge circuit which operates upon detection of completion of a write operation and stops the operation upon detection that the bit line is precharged to a high potential.
In the semiconductor memory, preferably, the second precharge circuit comprises: a first NAND gate to which a bit line signal is supplied; a first inverter to which a write control signal is supplied; a second NAND gate to which an output signal of the first NAND gate and an output signal of the first inverter are supplied; first and second PMOS transistors, both of which are disposed between a power source on a high potential side and a bit line, and have a gate connected to an output of the second NAND gate; and a third PMOS transistor which is provided between bit lines, and whose gate is connected to an output of the second NAND gate.
This object and other objects of the invention will become apparent from the following detailed description and the appended claims by referring to the ac

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