Method of manufacturing a CMOS transistor

Details Method of manufacturing a CMOS transistor Method of manufacturing a CMOS transistor

2000-06-30

2001-10-09

Le, Vu A. (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S199000, C438S218000, C438S230000, C438S231000, 43, 43

Reexamination Certificate

active

06300184

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to a method of manufacturing a dual gate CMOS transistor of a semiconductor device. More particularly, the present invention relates to a method of manufacturing a CMOS transistor by which ion implantation process is selectively performed to the gate formed region of a polysilicon film after a NMOS transistor region and a PMOS transistor region are defined in the process of manufacturing a CMOS transistor, thus it can obtain a reliable device by solving the problem occurring when polysilicon films doped with different impurities are simultaneously etched and the problem that a tungsten film is oxidized due to a selective oxidization process after forming a tungsten gate electrode.
1. Description of the Prior Art
Referring now to
FIGS. 1A through 1C
, a method of manufacturing a conventional CMOS transistor will be explained below.
First, referring to
FIG. 1A
, a trench is formed at a given region on a semiconductor device
101
. Then, a device separation film
102
is formed by oxidization process to separate a p-well region and an n-well region. Then, a NMOS transistor region and a PMOS transistor region are defined by means of ion implantation process using an ion implantation mask. Next, a gate oxide film
103
and a polysilicon film
104
are formed on the entire structure. By performing twice application process of a photosensitive film and patterning process, n-type impurity is implanted into the polysilicon film
104
of the NMOS transistor region and p-type impurity is implanted into the polysilicon film
104
of the PMOS transistor region, thus forming a dual polysilicon film.
As shown in
FIG. 1B
, after the photosensitive film pattern
105
is removed, a barrier metal layer
106
, a metal layer
107
and a nitride film
108
are sequentially formed on the entire structure. Tungsten is usually used as the metal layer
107
.
Referring now to
FIG. 1C
, selected regions of the nitride film
108
, the metal layer
107
, the barrier metal layer
106
and the polysilicon film
104
are etched to form a gate electrode. Then, a oxide film
109
is formed from the side wall of the polysilicon film
104
to the upper portion of the semiconductor substrate
101
by means of a selective oxidization process, so that the tungsten film used as the metal layer
107
is not oxidized. Next, after low concentration impurity ion implantation process, a conventional method of manufacturing a CMOS is performed.
However, in the conventional CMOS manufacturing process as explained above, the gate forming method has a problem of an abnormal oxidization phenomenon in which the metal layer (tungsten film) is expanded due to a subsequent process. This causes a problem that after forming a gate electrode, ions are not implanted into the edge of the gate electrode by the expanded portion of the gate electrode due to abnormal oxidization, in the a low concentration impurity ion implantation process being a subsequent process.
Also, in the conventional dual gate process, upon etching of the polysilicon film for forming the gate electrode, as impurities implanted into the polysilicon film of the NMOS transistor region and the PMOS transistor region are different each other, the etching rate are thus different. Accordingly, it causes a problem that the semiconductor substrate will be damaged, etc. Further, in order to prevent oxidization of tungsten used as the gate electrode, it has to use very expensive equipment only for use in selective oxidization process.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method of manufacturing a CMOS transistor of a semiconductor device by which reliability of a device can be improved by applying a semi damascene structure capable of implementing LDD oxidization, without the problem of different etching characteristics of the n-type polysilicon film and the p-type polysilicon film occurring in the process of etching the ploysilicon film upon formation of the dual gate electrode, and implementation of selective oxidization process.
A method of manufacturing a CMOS transistor according to the present invention is characterized in that it comprises the step of forming a device separation film a given region on a semiconductor substrate to define a PMOS transistor region and a NMOS transistor region; sequentially forming a gate oxide film, a polysilicon film and an oxide film and then removing said oxide on which gate will be formed to expose a given region of said polysilicon film; implanting different impurity ions into the polysilicon film of said exposed NMOS transistor and PMOS transistor; forming a spacer at the side wall of the etched oxide film on the portion in which said gate will be formed and then forming a tungsten nitride film on the entire structure; forming a tungsten film on the entire structure so that the portion in which said gate will be formed can be buried, and then remains a given portion of the portion in which said gate will be formed by blanket etching process; forming an insulating film on the entire structure and then remaining a nitride film on said tungsten film of the portion in which said gate will be formed by polishing process; removing said oxide film to remain a tungsten film, a nitride film and a spacer surrounding them, and then using them as a mask to etch said polysilicon film and said gate oxide film into which impurity are not implanted, thus forming a dual structure; forming an oxide film from said polysilicon film to on the underlying semiconductor substrate by means of selective oxidization process; and performing low concentration impurity ion implantation process and high concentration impurity ion implantation process after forming a spacer at the side wall of the gate to form a junction region.


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