Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2001-03-23
2001-12-25
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S154000, C365S203000
Reexamination Certificate
active
06333874
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device having normal and standby modes and also relates to a semiconductor integrated circuit and a mobile electronic unit including a device of that type.
A semiconductor memory device called a static random access memory (SRAM) is basically made up of flip-flops, and is easy to use because such a device needs no refreshing. An SRAM can also operate at a high speed and allows a large operation margin. By taking advantage of all these beneficial features, SRAMs are often used as memories for mobile electronic units, for example. In addition, as transistors have their sizes further reduced over the last couple of years, mobile electronic units have also been downsized.
However, the smaller a transistor, the lower its break-down voltage. Accordingly, a transistor of a very small size should be operated with its operating voltage lowered. Furthermore, to enable a transistor to operate at a low voltage without sacrificing its operating speed, the threshold voltage of the transistor needs to be reduced. For that reason, small-sized mobile electronic units, including cell phones, which are normally driven by battery, use transistors with a low threshold voltage. However, if the threshold voltage of a transistor is too low, then the transistor with that low threshold voltage cannot be cut off completely, thus allowing some leakage current to flow. In that case, an increased amount of current is dissipated in vain in a standby mode.
A battery-driven mobile electronic unit of a small size is required to operate at a low voltage and with low power dissipation. As for a cell phone, in particular, it is one of the key features determining its market value how long the cell phone can hold its standby state. And to make the stand-by state as long as possible, the amount of current dissipated in the standby mode should be minimized.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a semiconductor memory device that dissipates a reduced amount of current in its standby mode.
A semiconductor memory device according to an aspect of the present invention has normal and standby modes and includes: array of memory cells; a plurality of word lines; a plurality of bit lines; a plurality of access transistors; and potential difference generating means. In the memory array, multiple memory cells are arranged in columns and rows. Each of the word lines is associated with one of the rows. Each of the bit lines is associated with one of the columns. Each of the access transistors is provided for an associated one of the memory cells, connected between a data retention node of the associated memory cell and one of the bit lines that is associated with the memory cell, and receives, at its gate, a voltage on one of the word lines that is associated with the memory cell. And the potential difference generating means generates a negative potential difference between the gate and source of one of the access transistors while the device is in the standby mode. The access transistor is connected to a data retention node storing logical-one-level or logical-zero-level data thereon.
In one embodiment of the present invention, if the potential difference between the gate and source of the access transistors is 0 V, a current of 100 pA/&mgr;m or more flows between the drain and source of the access transistors.
While the inventive semiconductor memory device is in the standby mode, a negative potential difference is generated between the gate and source of one of the access transistors that is connected to a data retention node storing logical-one-level or logical-zero-level data thereon. As a result, the amount of leakage current, flowing from the logical-one-level data retention node into one of a pair of bit lines via the access transistor or from the other bit line into the logical-zero-level data retention node via the access transistor, can be reduced.
In another embodiment of the present invention, the potential difference generating means preferably includes potential holding means for holding a potential on the bit lines at a predetermined positive level while the device is in the standby mode.
In the semiconductor memory device of this embodiment, the potential level on the bit lines is higher than that on the word lines during the standby mode. Accordingly, a negative potential difference is generated between the gate and source of one of the access transistors that is connected to the logical-one-level data retention node. As a result, the amount of leakage current, flowing from the logical-one-level data retention node into the bit line via the access transistor, can be reduced. In addition, by holding the potential on the bit lines at such a level as not causing the problem of gate-induced-drain-leakage (GIDL) current, the GIDL current problem is avoidable.
In still another embodiment, the potential difference generating means preferably includes means for allowing the bit lines to be floating while the device is in the standby mode.
In the semiconductor memory device of this embodiment, the leakage current, flowing from the logical-one-level data retention node into the bit line via the access transistors, precharges the bit lines during the standby mode. As a result, the potential on the bit lines can be held at a positive level.
In yet another embodiment, the potential difference generating means preferably includes word line driving means for supplying a negative voltage onto the word lines while the device is in the standby mode.
In the semiconductor memory device of this embodiment, the potential level on the word lines is lower than the potential level at the logical-zero-level data retention node during the standby mode. Accordingly, a negative potential difference is generated between the gate and source of one of the access transistors that is connected to the logical-zero-level data retention node. As a result, the amount of leakage current, flowing from the bit line into the logical-zero-level data retention node via the access transistor, can be reduced.
A semiconductor memory device according to another aspect of the present invention has normal and standby modes and includes: array of memory cells; a plurality of word lines; a plurality of bit lines; a plurality of access transistors; word line driving means; and precharge means. In the memory array, multiple memory cells are arranged in columns and rows. Each of the word lines is associated with one of the rows. Each of the bit lines is associated with one of the columns. Each of the access transistors is provided for an associated one of the memory cells, connected between a data retention node of the associated memory cell and one of the bit lines that is associated with the memory cell, and receives, at its gate, a voltage on one of the word lines that is associated with the memory cell. The word line driving means activates one of the word lines, which is associated with one of the memory cells that is to be accessed. And the precharge means precharges the bit lines to a supply voltage level during a predetermined period before the memory cell is accessed. While the device is in the standby mode, the word line driving means supplies a negative voltage onto the word lines, and the precharge means electrically disconnects the bit lines from a power supply node receiving a supply voltage.
While the inventive semiconductor memory device is in the standby mode, no power is supplied from the power supply node to the bit lines that are electrically disconnected from the power supply node. Accordingly, the potential level on the bit lines is lower than the supply voltage level, and is normally stabilized at around an intermediate potential level, which is half as high as the supply voltage level. As a result, the source-drain voltage of the access transistors, connected to the data retention nodes, can be lowered to such a level as not causing the GIDL current problem.
Thus, the inventive semiconductor memory device ca
Dinh Son T.
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
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