Semiconductor memory device and redundancy circuit, and...

Details Semiconductor memory device and redundancy circuit, and... Semiconductor memory device and redundancy circuit, and...

2000-12-21

2001-12-11

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S225700

Reexamination Certificate

active

06330199

ABSTRACT:

The present application claims priority under 35 U.S.C. 119 to Korean Application No. 2000-13711 filed on Mar. 17, 2000, which is hereby incorporated by reference in its entirety for all purposes.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device and a redundancy circuit, and a method thereof which can increase the redundancy efficiency during performing of a column redundancy operation.
2. Description of the Related Art
A conventional semiconductor memory device replaces a column select signal line connected to a defective partial block of a memory with a redundant column select signal line connected to a redundant partial block of each of memory cell array blocks, when partial blocks of a plurality of memory cell array blocks are defective. Here, a partial block is a block including memory cells connected to one column select signal line. However, in this case a partial block of not only a defective block, but also partial blocks of other memory cell array blocks connected to the same column select signal line as the defective partial block, are replaced with a redundant partial block.
For example, in a case that the number of redundant partial blocks of each of memory cell array blocks is one and there is a defect in one partial block of one memory cell array block among a plurality of memory cell array blocks, the conventional semiconductor memory device replaces a column select signal line connected to a defective partial block with a redundant column select signal line connected to a redundant partial block. Then, partial blocks of other memory cell array blocks connected to the defective column select signal line are also replaced with a redundant partial block.
However, if there are defects in other partial blocks of other memory cell array blocks, this semiconductor memory device cannot be repaired. That is, there is a problem that the conventional semiconductor memory device can not be repaired when the number of defective column select signal lines that occur in all the memory cell array blocks exceeds the number of redundant column select signal lines. This is because a redundancy circuit of the conventional semiconductor memory device is configured so that a column select signal line connected to partial blocks located in the identical position among a plurality of memory cell array blocks is replaced with a redundant column select signal line. This problem may occur in a semiconductor memory device of a stack bank structure. Therefore, a conventional semiconductor memory device has a problem that redundancy efficiency is poor with respect to performing column redundancy.
A redundancy circuit of a conventional semiconductor memory device directed to solving the above problem is disclosed in U.S. Pat. No. 5,325,334, entitled “Column Redundancy Circuit of a Semiconductor Memory Device”. This circuit is configured to select a defective block by a block selection control circuit during performing of a column redundancy operation, and to generate a redundant enable signal by programming a column address of a defective block.
The above noted redundancy circuit of the conventional semiconductor memory device can increase the redundancy efficiency by performing a redundancy operation selectively by use of a block select signal, so as to select defective memory cell array blocks. However, the above noted redundancy circuit of the conventional semiconductor memory device has a problem in that the redundancy efficiency increases for regular defects, but decreases for irregular defects.
A redundancy method of a conventional semiconductor memory device will now be described as follows with reference to the accompanying drawings.
FIG. 1
is a configuration of a memory cell array of a conventional semiconductor memory device, including eight memory cell array blocks BLA, BLB, BLC, BLD, BLE, BLF, BLG and BLH, and a word line WL is arranged in a horizontal direction in each of the eight memory cell array blocks. A local data input/output line LIO is arranged between neighboring memory cell array blocks, and column select signal lines CSL
1
, CSL
2
, . . . and CSLn and a redundant column select signal line RCSL are arranged in a vertical direction.
In
FIG. 1
, partial blocks indicated by a dotted line are partial blocks of each of the memory cell array blocks and are connected to column select signal lines CSL
1
, CSL
2
, . . . and CSLn. Partial blocks indicated by a solid line are redundant partial blocks and are connected to the redundant column select signal line RCSL. Each of memory cell array blocks BLA, BLB, BLC, BLD, BLE, BLF, BLG and BLH respectively comprises n memory cell partial blocks and redundant partial blocks BLA
1
, . . . , BLAn, RBLA; BLB
1
, . . . , BLBn, RBLB; . . . and BLH
1
, . . . , BLHn, RBLH. A redundancy method of the prior semiconductor memory device will be described as follows using FIG.
1
.
If a memory cell of a partial block BLA
2
of a memory cell array block BLA connected to a column select signal line CSL
2
is defective, a column select signal line CSL
2
is replaced with a redundant column select signal line RCSL when a corresponding column address is inputted, without regard to whichever block is selected among memory cell array blocks BLA, BLB, BLC, BLD, BLE, BLF, BLG and BLH. However, in a case that a partial block BLA
1
of a memory cell array block BLA and a partial block BLB
2
of a memory cell array block BLB are defective at the same time, only one line of a column select signal line CSL
1
or a column select signal line CSL
2
can be replaced with a redundant column select signal line RCSL. That is, partial blocks BLA
1
, BLB
1
, . . . and BLH
1
connected to a column select signal line CSL
1
are replaced with redundant partial blocks RBLA, RBLB, . . . and RBLH respectively, or partial blocks BLA
2
, BLB
2
, . . . and BLH
2
connected to a column select signal line CSL
2
are replaced with redundant partial blocks RBLA, RBLB, . . . and RBLH respectively.
Therefore, in a case that there is only one redundant column select signal line RCSL as shown in
FIG. 1
, one column select signal line of all the memory cell array blocks is replaced with a redundant column select signal line, and other column select signal lines can not be replaced with a redundant column select signal line.
FIG. 2
is a configuration of an embodiment of a memory cell array block BLA and a peripheral circuit thereof shown in
FIG. 1
, wherein a partial block BLA
1
comprises memory cells MC connected between four bit line pairs BL
1
, BL
1
B; BL
2
, BL
2
B; BL
3
, BL
3
B and BL
4
, BL
4
B and word lines WL
1
, . . . and WLn. The peripheral circuit of the partial block BLA
1
comprises sense amplifiers
20
-
1
,
20
-
2
,
20
-
3
and
20
-
4
for amplifying input/output data that are connected to four bit line pairs BL
1
, BL
1
B; BL
2
, BL
2
B; BL
3
, BL
3
B and BL
4
, BL
4
B respectively, and comprises data input/output gates
22
-
1
,
22
-
2
,
22
-
3
and
22
-
4
which are connected between sense amplifiers
20
-
1
,
20
-
2
,
20
-
3
and
20
-
4
and local data input/output line pairs LIO
1
, LIO
1
B; LIO
2
, LIO
2
B; LIO
3
, LIO
3
B and LIO
4
, LIO
4
B and which are for transmitting data in response to a signal applied to a column select signal line CSL
1
. The configuration of the other partial blocks and peripheral circuits are the same as the configuration of partial block BLA
1
and the corresponding peripheral circuit.
A data input/output operation in
FIG. 2
will be described as follows. If a memory cell array BLA is selected and a signal applied to a column select signal line CSL
1
is activated, data input/output gates
22
-
1
,
22
-
2
,
22
-
3
and
22
-
4
of partial block BLA
1
are turned on and data is transmitted between bit line pairs BL
1
, BL
1
B; BL
2
, BL
2
B; BL
3
, BL
3
B and BL
4
, BL
4
B of the partial block BLA
1
and local data input/output line pairs LIO
1
, LIO
1
B; LIO
2
, LIO
2
B; LIO
3
, LIO
3
B and

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