Method of manufacturing dynamic random access memory cell

Details Method of manufacturing dynamic random access memory cell Method of manufacturing dynamic random access memory cell

2000-12-11

2001-12-11

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S253000, C438S396000, C438S399000

Reexamination Certificate

active

06329244

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89125786, filed Dec. 4, 2000.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing dynamic random access memory (DRAM) cell.
2. Description of Related Art
Dynamic random access memory (DRAM) is a type of volatile memory. Although reading from and writing to a DRAM cell is quite complicated and the design of peripheral circuits is quite intricate, each DRAM cell consists only of a transistor and capacitor. Hence, an array of the device can be put together on a silicon chip to produce a highly integrated memory circuit at a low cost. Nowadays, DRAM is one of the most widely adopted memory components.
A capacitor is a critical device in the storage of data in each DRAM cell. A DRAM capacitor capable of storing a larger number of electric charges is less vulnerable to noise corruption when stored data within the DRAM is read out. There are a number of means to increase the storage capacity of a capacitor. For example, the effective surface area of a capacitor can be increased to provide more space for accumulating electric charges. However, as the level of integration continues to increase, new methods and structures must be sought to obtain a relatively constant capacitance.
FIGS. 1A through 1E
are schematic cross-sectional views showing the progression of steps for manufacturing a conventional DRAM cell.
As shown in
FIG. 1A
, a substrate
100
having a transistor therein is provided. A first dielectric layer
101
is formed over the substrate
100
and then a bit line
103
is formed over the first dielectric layer
101
. A second dielectric layer
102
is formed over the bit line
103
and the first dielectric layer
101
. Using photolithographic technique, a patterned first photoresist layer
104
is formed over the second dielectric layer
102
.
As shown in
FIG. 1B
, a node contact opening
106
is formed in the second dielectric layer
102
using the first photoresist layer
104
as an etching mask. The first photoresist layer
104
is removed. Polysilicon material is deposited into the node contact opening
106
to form a polysilicon layer
108
. A silicon nitride layer
110
is formed over the second dielectric layer
102
and then a third dielectric layer
112
is formed over the silicon nitride layer
110
. A second patterned photoresist layer
114
is formed over the third dielectric layer
112
.
As shown in
FIG. 1C
, the second dielectric layer
112
and the silicon nitride layer
110
are sequentially etched using the second patterned photoresist layer
114
as a mask to form an opening
116
. The second photoresist layer
114
is removed. Polysilicon material is deposited into the opening
116
and over the second dielectric layer
112
to form a polysilicon layer
118
. A silicon oxide layer
120
that fills the opening
116
is formed over the polysilicon layer
118
.
As shown in
FIG. 1D
, the silicon oxide layer
120
is etched back until the polysilicon layer
118
is exposed. The polysilicon layer
118
is etched until the third dielectric layer
112
is exposed.
As shown in
FIG. 1E
, the third dielectric layer
112
and the silicon oxide layer
120
are removed using the silicon nitride layer
110
as an etching stop layer. Ultimately, the polysilicon layer
108
at the bottom section of the opening
116
is exposed to serve as the lower electrode of a capacitor.
In a conventional method, the process of forming the node contact and the lower electrode opening requires two masking steps. The additional process not only increases production cost, the chance of contaminating the silicon chip increases as well. Moreover, the process of forming the node contact opening requires proper alignment. Any misalignment may lead to circuit connection errors.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a method of manufacturing a dynamic random access memory (DRAM) cell that reduces the number of masking steps and hence reduces possibility of contamination and lowers production cost. Furthermore, the method can prevent circuit connection problems due to node contact opening misalignment.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of manufacturing a dynamic random access memory cell. A substrate having a transistor therein is provided. A first dielectric layer is formed over the substrate and the transistor. A bit line having a cap layer thereon is formed over the first dielectric layer. A protective layer is formed over the substrate covering the bit line. A second dielectric layer is formed over the protective layer. The second dielectric layer is etched in a self-aligned process. The etching continues penetrating the protective layer and the first dielectric layer until the substrate is exposed so that a node contact opening and an opening for forming the lower electrode of a capacitor are formed at the same time. Thereafter, polysilicon material is deposited into the node contact opening and the lower electrode opening to form a polysilicon layer. The upper surface of the polysilicon layer is slightly below the lower electrode opening. A spacer is formed on the sidewalls of the lower electrode opening above the polysilicon layer. Using the spacers as a mask, the polysilicon layer is etched to form a lower electrode with a recess groove above the node contact opening. The second dielectric layer and the spacers are removed. To complete the fabrication of the DRAM cell capacitor, a dielectric layer is formed over the lower electrode and then an upper electrode is formed over the dielectric layer.
In this invention, since a self-aligned method is used to form the node contact opening, the application of mask and photoresist is not required. Therefore, the number of processing steps and hence production cost and time are reduced. In addition, the chance of contaminating the device is minimized. Moreover, there is no need to worry about contact opening misalignment because a self-aligned process is used. Hence, tolerance for the fabrication process is improved. Furthermore, the space between the bit lines is utilized to form part of the lower electrode and hence effective surface area of the capacitor is increased. Another advantage of using the space between the bit lines as part of the lower electrode is that capacitor height can be reduced. In brief, the invention is able to increase the effective surface of a capacitor. Ultimately, the level of integration can be increased without compromising charge storage capacity of the capacitor.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 6074955 (2000-06-01), Lin et al.
patent: 6150213 (2000-11-01), Luo et al.
patent: 6174782 (2001-01-01), Lee

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