Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-09-03
2001-02-06
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S399000
Reexamination Certificate
active
06184080
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to dynamic random access memory (DRAM) devices and particularly relates to a DRAM apparatus wherein the contacts for the storage nodes, the bit lines and the periphery circuits can all be formed simultaneously, and to a method for forming such a device.
BACKGROUND OF THE INVENTION
Continued growth in the capacity of dynamic random access memory (DRAM) technology can be enhanced by minimizing the size of individual DRAM cells. As technology develops, DRAM devices need to store more bits of information, use less power per bit of stored information and have the individual memory cells containing the stored bits occupy less area on the semiconductor chip. Furthermore, it is desirable to simplify the manufacturing process for DRAM devices, and thereby lower the cost of such devices. Each cell in such a device typically comprises a MOS pass transistor and a storage node forming one plate of a storage capacitor.
In order to simplify the manufacturing process and minimize the cell size of DRAM cells, there are three requirements which should be simultaneously satisfied. These include the simultaneous formation of the storage node contacts, the bit line contacts, and the contacts in the periphery circuit; the formation of the bit lines in a straight line configuration; and the use of the bit lines as wiring for the periphery circuits.
It has proven difficult to meet the requirement of simultaneous formation of the storage node, bit line and periphery circuit contacts by simple simultaneous formation of these contacts. An inward portion of the storage node contact is normally formed of either n-type or p-type doped polysilicon. This is due to the fact that employing metal in these locations is generally not desirable, since it would reduce the data retention time on the storage node, which would in turn require more frequent refreshing for the DRAM. Conversely to the situation for the storage node contacts, the contacts for the periphery circuit generally do require metal at inward portions, in order to form ohmic contacts for both n-type and p-type active regions. Doped polysilicon normally cannot be employed in this application.
Reference should now be had to
FIGS. 1
,
2
and
3
.
FIG. 1
shows a top plan view of a prior art DRAM device, while
FIG. 2
shows a cross section taken along line II—II in FIG.
1
and
FIG. 3
shows a cross section taken along line III—III in FIG.
1
. The prior art device is designated generally as
10
. It includes a plurality of word lines
12
and a plurality of bit lines
14
. Also included are a plurality of storage nodes
16
and a plurality of active regions
18
. A first type of contact is designated as
20
and a second type of contact is designated as
22
. With particular reference to
FIGS. 2 and 3
, storage node
16
is interconnected to active region
18
through the second type of contact
22
, an intermediate polysilicon pad
24
, and the first type of contact
20
. Similarly, bit line
14
is interconnected to active region
18
through the second type of contact
22
, intermediate polysilicon pad
24
, and the first type of contact
20
. Isolators
26
are also shown in
FIGS. 2 and 3
. Note that a cell over bit line (COB) type of device is shown in the figures.
The prior art device shown in
FIGS. 1-3
is subject to several problems. First, extra manufacturing steps are required. For example, an additional photolithography process is required for the formation of the first type of contact
20
and the pad
24
. Additional deposition and etching processes are also required in conjunction with the photolithography process. Thus, manufacturing cost is increased. Further, the height of the second type of contact
22
from the substrate on which the active region
18
is formed to the bit lines
14
(which are also used as wiring in the periphery circuits) is increased due to the additional thickness needed for the first type of contact
20
and the polysilicon pad
24
. This has caused difficulty in forming good ohmic contacts, that is, the second type of contact
22
, in the periphery circuits.
Another prior device is disclosed in the article by Y. Kohyama et al. entitled “A Fully Printable, Self-aligned and Planarized Stacked Capacitor DRAM Cell Technology for 1 Gbit DRAM and Beyond,” 1997 Symposium on VLSI Technology Digest of Technical Papers 17. This device employs polysilicon plugs with a so-called “Gate SAC” mask. The masked regions are identical in size and shape to the active areas. There is no provision for having a reduced contact diameter so as to prevent misalignment between the contacts (for the storage nodes, e.g.) and the polysilicon plugs, nor is there provision to prevent shorting together of some of the plugs due to alignment errors during photolithography.
SUMMARY OF THE INVENTION
Therefore, a need has arisen for a DRAM device which is designed such that the storage node contacts, bit line contacts, and the contacts for the periphery circuits can be formed simultaneously. Further, there is a need for a method of forming such a device. The present invention provides such a device, which results in simplified manufacturing and less distance between the substrate and periphery circuit wiring, and which is tolerant of misalignment errors during manufacturing.
In accordance with the present invention, a dynamic random access memory device comprises a substrate formed of a semiconductor material; a plurality of substantially parallel word lines; a plurality of substantially parallel bit lines; a plurality of unitary bit line contacts; a plurality of storage nodes; and a plurality of unitary storage node contacts. The plurality of active regions extend outwardly from the substrate, which is formed of semiconductor material, and each active region has an outer surface and a longer and a shorter dimension when viewed in plan. The plurality of substantially parallel word lines are located outwardly from the active regions in a direction substantially parallel to the shorter dimension of the active regions and substantially perpendicular to the longer dimension of the active regions. The word lines are electrically isolated from each other, and two of the word lines are associated with each of the active regions. Further, two of the word lines are positioned between adjacent active regions.
The plurality of substantially parallel bit lines are located outwardly from the word lines and are substantially perpendicular to the word lines. The bit lines are located between adjacent ones of the active regions when viewed in plan, and are electrically isolated from each other. Each of the bit lines has an inward-projecting portion (or contact) associated with each of the active regions. The plurality of unitary bit line contacts (or contact plugs) extends from the inward-projecting portions of the bit lines to associated ones of the active regions and is offset when viewed in plan view and also when viewed in cross-section perpendicular to the bit lines. This feature aids in the simultaneous formation of the bit line contacts.
The plurality of storage nodes extend outwardly of the bit lines, and each of the storage nodes has a longer and a shorter dimension when viewed in plan. The longer dimension of the storage nodes is generally parallel to the longer dimension of the active regions and the shorter dimension of the storage nodes is generally parallel to the shorter dimension of the active regions. At least substantial portions of the storage nodes are located substantially directly outwardly of the active regions when viewed in plan and are also located between the bit lines when viewed in plan. Each of the storage nodes has an inward-projecting portion (or contact) associated with a given one of the active regions, with two of the storage nodes being associated with each of the active regions.
One of each of the storage node contacts (or contact plugs) extends inwardly from each of the inwardly-projecting portions (or contacts) of the storage nodes to a corresponding
Brady III W. James
McLarty Peter K.
Nguyen Tuan H.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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