Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-11-02
2001-02-27
Tu, Christine T. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S726000, C703S022000
Reexamination Certificate
active
06195776
ABSTRACT:
FIELD OF THE INVENTION
The field of the present invention pertains to the field of automatic test pattern generation for use with electronic design automation tools. More particularly, aspects of the present invention pertain to testability analysis and test methodology analysis for use in the design of complex integrated circuits with computer aided design (CAD) tools.
BACKGROUND OF THE INVENTION
Computer systems, software applications, and the devices and processes built around them are continually growing in power and complexity. Society's reliance on such systems is likewise increasing, making it critical that the systems obey the properties that their designers intended. Typically, the more powerful and complex the system, the greater its utility and usefulness. However, as these computer and software implemented systems and processes become more powerful, detecting and correcting flaws within the systems becomes increasingly difficult.
The development of ASICs (application specific integrated circuits) and other complex integrated circuits with the aid of CAD tools is referred to as electronic design automation, or EDA. Design, checking, and testing of large-scale integrated circuits are so complex that the use of programmed computer systems are required for realization of normal circuits. This is partly because the integrated devices are inherently complex and partly because the circuit design needs to be decomposed into simpler functions which are recognized by the CAD tool. It is also partly because considerable computation is required in order to achieve an efficient layout of the resultant network. The result of the computerized design process is a detailed specification defining a complex integrated circuit in terms of a particular technology. This specification can be regarded as a template for the fabrication of the physical embodiment of the integrated circuit using transistors, routing resources, etc.
Integrated circuit designs can be represented in different levels of abstraction, such as the register transfer level (RTL) and the logical level, using a hardware description language (HDL), also called high level design language. Two exemplary forms of HDL are Verilog and VHDL. The integrated circuit can be represented by different layers of abstractions (e.g., behavioral levels, structural levels and gate levels). An RTL level is an intermediary level of abstraction between the behavioral and structural levels. HDL descriptions can represent designs of all these levels.
The behavior levels and RTL levels consist generally of descriptions of the circuit expressed with program-like constructs, such as variables, operators conditional loops, procedures, and functions. At the logic level, the descriptions of the circuit are expressed with Boolean equations. The HDL can be used along with a set of circuit constraints as an input to a computer-implemented compiler (also called a “silicon compiler”). The computer-implemented compiler program processes this description of the integrated circuit and generates therefrom a detailed list of logic components and the interconnections between these components. This list is called a “netlist.” The components of a netlist can include primitive cells such as full-adders, NAND gates, NOR gates, XOR gates, latches, and D-flip flops, etc., and their interconnections can be used to form a custom design.
In processing the HDL input, the compiler first generates a netlist of generic primitive cells that are technology independent. The compiler then applies a particular cell library to this generic netlist (this process is called mapping) in order to generate a technology-dependent mapped netlist. The mapping process converts the logical representation which is independent of technology into a form which is technology dependent. The mapped netlist has recourse to standard circuits, or cells, which are available within a cell library forming a part of the data available to the computer system.
Compiler programs and mapping programs are well known in the art, and several of these systems are described in U.S. Pat. No. 5,406,497, by Altheimer et al.
As ASICs and other complex integrated circuits have become more complex and more dense, they have become progressively harder to test in order to ensure correct and complete functionality. For example, with current technology, as the number of gates and transistors increase, the time which an ASIC emerging from a fabrication process line spends in testing increases as well. This increase incurs an additional cost on ASIC manufacturing. The testing cost can be very significant for the latest and largest memories. In addition, as more complex systems-on-a-chip devices proliferate, which, for example, integrate complex logic units (integer units, floating point units, memory, etc.) into a single chip, and as newly-designed processors begin to take advantage of the ability to integrate large quantities of memory on-chip, it has become necessary to increase the comprehensiveness, efficiency, and accuracy of the design checking and testing schemes utilized to ensure proper operation of these devices (e.g., ASICs, complex integrated circuits, field programmable gate arrays, etc.).
Thus, an increasingly important part of the logic synthesis and testing process involves designing ASICs and other complex integrated circuits for inherent testability. Programs that aid in the testability process of logic synthesis are called design for test (DFT) processes. As part of DFT, it is well known to take the mapped netlist generated from a compiler and add and/or replace certain memory cells and associated circuitry with special memory cells that are designed to allow the application of test vectors to certain logic portions of the integrated circuit. The act of applying test vectors is called stimulation of the design, and the special memory cells and associated circuitry are referred to as DFT implementations. Issues concerning controllability deal with facilitating the application of the test vectors to the circuitry to be tested. The same memory cells can be used to capture the output of the circuitry for observation and compare this output to the expected output in an effort to determine if circuit (e.g., manufacturing) defects are present.
The portions of an integrated circuit that are designed to perform its intended or expected operational function are called its “mission mode” circuitry, while the portions added to the integrated circuit to facilitate testability are called “test mode” circuitry or DFT implementations. The resultant circuit, therefore, has two functional modes, mission and test.
Prior art
FIG. 1A
shows an exemplary flow chart diagram of a typical prior art logic synthesis process, including a DFT process. The processes
200
described with respect to this flow chart is implemented within a computer system in a CAD environment. High level design language (HDL) descriptions of the integrated circuit enter at block
201
. Accompanying the HDL
201
is a set of performance constraints applicable to the design which typically include timing, area, power consumption, and other performance related limitations that the compiler (e.g., in step
202
) will attempt to satisfy when synthesizing the integrated circuit design. These constraints can also include non-performance related constraints such as structural and routing constraints. In step
202
, the HDL descriptions of the integrated circuit are compiled. The compiler (also called an HDL compiler, RTL synthesizer, or architectural optimizer) inputs the HDL
201
description and generates therefrom a technology independent or “generic” netlist. The generic netlist is then compiled using logic optimization procedures and a mapping procedures which interface with a technology dependent cell library
204
(e.g., from LSI, VLSI, TI or Xilinx technologies, etc.). The cell library
204
contains specific information regarding the cells of the specific technology selected such as the cell logic, number of gates, area consumption, power consu
Ganesan Hari
Ruiz Robert
Synopsys Inc.
Tu Christine T.
Wagner , Murabito & Hao LLP
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