Flash memory device and fabrication method thereof

Details Flash memory device and fabrication method thereof Flash memory device and fabrication method thereof

1998-02-09

2001-02-13

Saadat, Mahshid (Department: 2815)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S257000, C438S261000, C438S304000, C438S305000, C438S596000

Reexamination Certificate

active

06187636

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to memory devices and, in particular, to a flash memory device and a fabrication method thereof.
2. Background of the Related Art
FIG. 1
illustrates a related art Floating-gate Tunneling Oxide (FLOTOX) Electrically Erasable and Programmable Read Only Memory (EEPROM). An active region
1
a
and a field region
1
b
are formed on the upper surface of a semiconductor substrate
1
. In the semiconductor substrate
1
, source and drain regions
2
and
3
are formed. A gate insulation layer
4
and a tunnel insulation layer
5
are formed within the active region
1
a
of the semiconductor substrate
1
. A first conductive layer (floating gate)
6
is formed on the upper surfaces of the gate insulation layer
4
and the tunnel insulation layer
5
. An interlayer insulation film
7
is formed on the upper surface of the first conductive layer
6
. A second conductive layer (control gate)
8
is formed on the upper surface of the interlayer insulation film
7
. An insulation film
9
is formed on the upper surfaces of the semiconductor substrate
1
and the second conductive layer
8
.
In operation, twenty volts (20V) is supplied to the control gate
8
and zero volts (0V) is supplied to the drain
3
. The source
2
and the substrate
1
are connected to ground. Electrons are injected into the floating gate
6
from the drain
3
through the tunnel insulation layer
5
via a Folwer-Nordheim (FN) tunneling effect. Electrons accumulate in the floating gate
6
, the threshold voltage of the device increases, and the intensity of the electric field, which is applied from the control gate
8
to the drain
3
, increases.
To erase the data from the FLOTOX EEPROM, the source
2
and the semiconductor substrate
1
are connected to ground, zero volts is supplied to the control gate
8
and twenty volts are supplied to the drain
3
. Electrons accumulated in the floating gate
6
are moved into the drain region
3
through the tunnel insulation layer
5
via the FN tunneling effect. Since the number of electrons in the floating gate
6
decrease, the threshold voltage of the FLOTOX EEPROM decreases, and the intensity of the electric field, which is applied from the drain
3
to the control gate
8
, also decreases.
The related art FLOTOX EEPROM requires a high voltage during programming and data erasing operations, and a high substrate current is generated due to the high voltage during data erasing operations. As a result, the characteristics of the FLOTOX EEPROM and the tunnel insulation layer
5
are quickly degraded.
In addition, due to the high substrate current generated, it is not possible to erase the data in the related art FLOTOX EEPROM using a 5-volt power source. Furthermore, it is not possible to perform a self-aligning process during the fabrication process for the related art FLOTOX EEPROM.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a flash memory device and a flash memory fabrication method that overcome the aforementioned problems encountered in the related art.
It is another object of the present invention to perform a data erasure at a low voltage.
It is another object of the present invention to simplify the fabrication process of the memory device through a self-aligning process.
To achieve the above objects, there is provided a flash memory device comprising: (1) a semiconductor substrate; (2) a source region and a drain region in the semiconductor substrate; (3) a first insulation layer formed on the semiconductor substrate; (4) a first conductive layer formed on a portion of the first insulation layer; (5) first and second conductive sidewall spacers positioned adjacent to first and second sidewalls of the first conductive layer, respectively; (6) a second insulation layer formed on the first and second sidewall conductive sidewall spacers; and (7) a second conductive layer formed on the insulation layer, the second conductive layer in electrical contact with the first conductive layer.
To achieve the above objects, there is also provided a flash memory device fabrication method, which comprises the steps of: (1) forming a first insulation layer on a semiconductor substrate; (2) forming a first conductive layer pattern on a portion of the first insulation layer; (3) forming low density impurity regions in the semiconductor substrate; (4) forming a second insulation layer on sidewalls of the first conductive layer pattern; (5) forming, on each of the two sides of the first conductive layer pattern, a conductive sidewall spacer on the second insulation layer and the first insulation layer; (6) forming high density impurity regions in the semiconductor substrate; (7) forming a third insulation layer that covers the conductive sidewall spacers and that contacts the first and second insulation layers; and (8) forming a third conductive layer pattern on the first, second and third insulation layers, the third conductive layer pattern in electrical contact with the first conductive layer pattern.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.


REFERENCES:
patent: 4925807 (1990-05-01), Yoshikawa
patent: 5478767 (1995-12-01), Hong
patent: 5599726 (1997-02-01), Pan
patent: 5620914 (1997-04-01), Hikida et al.
patent: 5654212 (1997-08-01), Jang
patent: 5716866 (1998-02-01), Dow et al.
patent: 5824584 (1998-10-01), Chen et al.
patent: 5920783 (1999-07-01), Tseng et al.
patent: 6001683 (1999-12-01), Lee
“Comparison and Trends in Today's Dominant E2Technologies”, S.K. Lai et al., IEDM Tech. Dig., pp. 580-583, (1986).

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