Non-volatile memory cell and methods of fabricating and...

Details Non-volatile memory cell and methods of fabricating and... Non-volatile memory cell and methods of fabricating and...

1999-11-19

2001-12-11

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S239000, C438S240000, C438S241000, C438S254000, C438S255000, C438S256000, C438S396000, C438S397000, C438S398000, C438S399000

Reexamination Certificate

active

06329240

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to non-volatile memory (NVM). More particularly, this invention relates to NVM fabricated by slightly modifying a conventional logic process. In the present application, a conventional logic process is defined as a semiconductor process that implements single-well or twin-well technology and uses a single layer of polysilicon. This invention further relates to a method of operating a non-volatile memory to ensure maximum data retention time.
BACKGROUND OF INVENTION
For system-on-chip (SOC) applications, it is desirable to integrate many functional blocks into a single integrated circuit. The most commonly used blocks include a microprocessor or micro-controller, SRAM blocks, non-volatile memory blocks, and various special function logic blocks. However, traditional non-volatile memory processes, which typically use stacked gate or split-gate memory cells, are not compatible with a conventional logic process. The combination of a non-volatile memory process and a conventional logic process results in much more complicated and expensive “merged non-volatile memory and logic” process to implement system-on-chip integrated circuits. This is undesirable because the typical usage of the non-volatile memory block in an SOC application is comparatively small compared with the overall chip size.
There are several prior art approaches to minimize the complexity of such a merged non-volatile memory and logic process. For example, U.S. Pat. No. 5,879,990 to Dormans et al. describes a process that requires at least two layers of polysilicon and two sets of transistors to implement both the normal logic transistors and the non-volatile memory transistors. This process is therefore more complex than a conventional logic process, which requires only a single layer of polysilicon.
U.S. Pat. No. 5,301,150 to Sullivan et al. describes a single poly process to implement a non-volatile memory cell. In this patent, the control gate to floating gate coupling is implemented using an n-well inversion capacitor. The control gate is therefore implemented using the n-well. An injector region must be coupled to the inversion layer in the n-well. The use of an n-well as the control gate and the need for an injector region result in a relatively large cell size.
U.S. Pat. No. 5,504,706 to D'Arrigo et al. describes a single poly process to implement a non-volatile memory cell that does not use an n-well as a control gate.
FIG. 1A
is a schematic diagram illustrating an array of non-volatile memory cells C00-C12 as described by D'Arrigo et al.
FIG. 1B
is a cross sectional view of one of these non-volatile memory cells. As shown in
FIG. 1A
, each of the memory cells contains a transistor
24
having a source connected to a virtual-ground (VG) line and a drain connected to a bit line (BL). The transistor
24
further has a floating gate
40
which is coupled to a word line (WL)
86
through a coupling capacitor. The coupling capacitor includes n+ region
80
, which is located under the floating gate
40
and which is continuous with the diffusion word line
86
. The capacitance of the coupling capacitor is significantly larger than the gate capacitance of the transistor to allow effective gate control of the transistor from the WL voltage levels. The n+ region
80
is formed by an additional implant to ensure good coupling during operations. This additional implant is not available in a standard logic process. The memory cells
24
are located inside a triple-well structure. More specifically, the memory cells are formed in a p− tank
78
, which in turn, is formed in an n− tank
76
, which in turn, is formed in p− well
74
. A p+ contact region
88
is located in p− tank
78
, and an n+ contact region
90
is located in n− tank
76
. The triple-well structure allows flexibility of biasing in operating the memory cell. More specifically, the triple-well structure allows a large negative voltage (typically −9 Volts) to be applied to the word line
86
(i.e., the control gate). Both the extra n+ implant and the triple-well are not available in a conventional logic process. Similarly, U.S. Pat. No. 5,736,764 to Chang describes a PMOS cell having both a select gate and a control gate, wherein additional implants are required underneath the control gate.
In addition, the above-described non-volatile memory cells use a relatively thick tunneling oxide (typically 9 nanometers or more). Such a thick tunneling oxide is not compatible with conventional logic processes, because conventional logic processes provide for logic transistors having a gate oxide thickness of about 5 nm for a 0.25 micron process and 3.5 nm for a 0.18 micron process.
Conventional non-volatile memory cells typically require special high voltage transistors to generate the necessary high voltages (typically 8 Volts to 15 Volts) required to perform program and erase operations of the non-volatile memory cells. These high voltage transistors are not available in a conventional logic process. These high voltage transistors are described, for example, in U.S. Pat. No. 5,723,355 to Chang et al.
U.S. Pat. No. 5,761,126 to Chi et al. describes a single poly EPROM cell that utilizes band-to-band tunneling in silicon to generate channel hot-electrons to be injected into a floating gate from a control gate. A relatively thin tunnel oxide can be used in this memory cell because of the enhanced electron injection. However, this memory cell only supports programming (i.e., electron injection into the floating gate). No support is provided to remove electrons from the floating gate (i.e., an erase operation is not supported).
The use of a thin gate oxide as tunneling oxide presents a challenge for achieving acceptable data retention time for non-volatile memory cells. A thin gate oxide is defined herein as a gate oxide layer having a thickness in the range of 1.5 nm to 6.0 nm. Although programming voltages may be reduced by the use of a thin gate oxide, the thin gate oxide will exacerbate cell disturbances. That is, the thin gate oxide will significantly increase the probability of spurious charge injection or removal from the floating gate during normal program, erase and read operations. This is due to the high electric field present in or near the thin gate oxide. As conventional logic processes scale down in geometry, the gate oxide thickness scales down proportionally. For example, a 0.25 micron process uses a 5 nm gate oxide thickness, a 0.18 micron process uses a 3.5 nm gate oxide thickness, and a 0.15 micron process uses a 3 nm gate oxide thickness. As a result, data-retention becomes a serious problem when using the standard gate oxide as the tunnel oxide in a non-volatile memory cell. U.S. Pat. No. 5,511,020 to Hu et al. describes data refreshing techniques to improve data retention time using very thin tunnel oxides.
It would therefore be desirable to implement a single-poly non-volatile memory cell using a conventional logic process, without requiring process modification and/or additional process steps.
It would also be desirable to have a method of operating non-volatile memory cells in conjunction with volatile memory arrays in a manner that minimizes disturbances from write, erasing and read operations, thereby improving the data retention time for the non-volatile memory cells.
SUMMARY
Accordingly, the present invention provides a non-volatile memory cell fabricated using a conventional logic process. The non-volatile memory cell uses a thin gate oxide (i.e., 1.5 nm to 6 nm) available in a conventional logic process. The non-volatile memory cell can be programmed and erased using relatively low voltages. The voltages required to program and erase can be provided by transistors readily available in a conventional logic process (i.e., transistors having a breakdown voltages in the range of 3 Volts to 7 Volts).
In one embodiment, the non-volatile memory cell includes a p-type semiconductor substrate and an n-well located in

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