Method of making EEPROM with trenched structure

Details Method of making EEPROM with trenched structure Method of making EEPROM with trenched structure

1998-03-27

2000-05-16

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438270, 438589, H01L 218247

Patent

active

060636645

ABSTRACT:
A new method of forming a trenched floating gate in the fabrication of a EEPROM memory cell is described. A trench is etched into a semiconductor substrate. Ions are implanted into the surface of the semiconductor substrate and into the semiconductor substrate surrounding the trench to form N+ regions. A gate oxide layer is grown over the surface of the semiconductor substrate and within the trench. The gate oxide within a tunneling window overlying one of the N+ regions is removed and a tunnel oxide is grown in the tunneling window. A polysilicon layer is deposited over the surface of the semiconductor substrate and within the trench and patterned to form a floating gate within the trench and on the surface of the substrate wherein the floating gate contacts the N+ region through the tunneling window.

REFERENCES:
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patent: 4835741 (1989-05-01), Baglee
patent: 5045490 (1991-09-01), Esquivel et al.
patent: 5180680 (1993-01-01), Yang
patent: 5429970 (1995-07-01), Hong
patent: 5480820 (1996-01-01), Roth et al.
patent: 5598367 (1997-01-01), Noble

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