Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-06-28
2001-10-16
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S255000
Reexamination Certificate
active
06303433
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a method of fabricating a capacitor.
2. Description of the Related Art
A memory function of a Dynamic Random Access Memory (DRAM) is carried out by controlling the voltage applied to the source region of a metal oxide semiconductor (MOS) transistor. Specifically, controlling the voltage applied to the MOS transistor entails controlling the flow of charges of a capacitor. In this manner, a read or a write operation is carried out, and thus the memory function of the DRAM is achieved. However, when the capacitor is operated, the charges in the capacitor are in a non-equilibrium state. In this non-equilibrium state, current leakage easily occurs. Therefore, it is necessary to refresh the capacitor periodically.
The refresh frequency depends on the charge-storage ability of the capacitor. As the storage ability of the capacitor increase, the refresh frequency for the capacitor is decreased. Thus, it would be advantageous to develop a capacitor having a high storage ability.
The storage ability of a capacitor can be increased by increasing the storage surface area of a capacitor or increasing the dielectric constant of a dielectric material. Since increasing the dielectric constant of the dielectric material usually involves material development, a long time is usually required for research and development. Thus, increasing the storage area of a capacitor by increasing the surface of bottom electrode is more expedient. The surface area of the bottom electrode can be increase by, for example, forming a hemispherical grained silicon (HSG) layer or increasing the height of the bottom electrode. In a fabrication process with a linewidth of 0.25 micrometers, or below, the surface area of a bottom electrode is increased not only by forming a HSG layer on the bottom electrode but also by increasing the height of the bottom electrode. However, the high bottom electrode often results in insufficient adhesion between the high bottom electrode and the contact node. This, in turn, causes the bottom electrode to lean or fall down. The quality of devices thus is degraded.
SUMMARY OF THE INVENTION
The invention provides a method of fabricating a contact node. A first dielectric layer is formed on the substrate. A second dielectric layer and a third dielectric layer are formed in sequence over the first dielectric layer. Portions of the first dielectric layer, the second dielectric layer, and the third dielectric layer are removed to form a contact opening which exposes a portion of the substrate. A conductive layer is formed in the contact opening. The third dielectric layer is removed to expose a portion of the conductive layer.
The invention also provides a capacitor of dynamic random access memory. A transistor is formed on a substrate. The transistor comprises a gate on the substrate and a source/drain region in the substrate. A first dielectric layer is formed on the substrate to cover the transistor. A second dielectric layer and a third dielectric layer are formed in sequence over the first dielectric layer. The first dielectric layer, the second dielectric layer, and the third dielectric layer are etched to form a contact opening which exposes a portion of the source/drain region. A conductive layer is formed in the contact opening and is electrically coupled with the source/drain region. A fourth dielectric layer is formed on the third dielectric layer and covers the conductive layer. Portions of the third dielectric layer and fourth dielectric layer are removed to form a storage node opening, which exposes a portion of the dielectric layer and a portion of the second dielectric layer. A bottom electrode is formed in the storage node opening to cover the exposed second dielectric layer and the conductive layer. The fourth dielectric layer and the third dielectric layer are removed to expose the second dielectric layer and the bottom electrode. A capacitor dielectric layer and a top electrode are formed in sequence to cover the bottom electrode.
In the present invention, the conductive layer serves as a node contact. After the third dielectric layer and the fourth dielectric layer are removed, the exposed conductive layer is used to provide support for the bottom electrode. The supported bottom electrode thus does not lean or fall down.
In comparison with the conventional method, in which only the top surface of the node contact is in contact with the bottom electrode, in the invention, the bottom electrode entirely covers the exposed conductive layer. Thus, the present invention increases the contact area between the node contact and the bottom electrode. Because of the increased contact area, the resistance between the node contact and the bottom electrode is decreased. The quality of the bottom electrode is enhanced. A high quality capacitor thus is obtained.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5851878 (1998-12-01), Huang
patent: 5888865 (1999-03-01), Lin
patent: 5907774 (1999-05-01), Wise
patent: 6037218 (2000-03-01), Dennison et al.
patent: 6080621 (2000-06-01), Wang et al.
Thomas Kayden Horstemeyer & Risley LLP
Tsai Jey
United Microelectronics Corp.
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