Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-09-06
2001-12-04
Bowers, Charles (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S258000, C438S259000, C438S261000, C438S262000, C438S266000, C257S316000
Reexamination Certificate
active
06326264
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device, and more specifically it relates to a semiconductor device in which a diffusion layer and an element separation insulation film are formed in a self-aligning manner, and to a method for manufacturing such as semiconductor device.
2. Description of the Related Art
In the past, with respect to a method for manufacturing a non-volatile semiconductor memory device such as a flash memory, there have been many disclosures of known technologies.
For example, one example of a method for manufacturing a flash memory in the past was disclosed in the Japanese Unexamined Patent Publication (KOKAI)No. 6-283721, the technological purport of which will be described with reference to
FIG. 12
(A) through FIG.
12
(G).
Specifically, in this method of the past, as shown in FIG.
12
(A), a known lithographic method is first used to form the element separations
201
and
202
, after which, as shown in FIG.
12
(B), a silicon oxide film
203
, which will serve as a tunnel film, is formed.
Next, as shown in FIG.
12
(C), polysilicon
204
, which will serve as a floating gate, and an ONO film
205
, which will serve as a capacitive film between the control gate and floating gate are formed, after which, as shown in FIG.
12
(D), lithography is used to pattern the ONO film
205
and the polysilicon
204
, and ion implantation is used to form the source and drain
213
and
214
.
Additionally, as shown in FIG.
12
(E), the drain side only is covered by a mash, and the source is subjected to ion implantation, so as to impart to the source a structure with a high withstand voltage.
Finally, as shown in FIG.
12
(E), resist is removed and, after oxidizing the diffusion layer and the side surface of the floating gate
204
, as shown in FIG.
12
(G) polysilicon
219
, which will serve as the control gate, is formed, patterning being done of the control gate
219
, the ONO film
205
, and the floating gate
204
, in this sequence, so as to form the memory cell.
In the method for manufacturing a non-volatile semiconductor memory device of the past, however, because the channel region and the element separation region are formed by separate lithography process steps, skew of position in the lithography process can cause a change in width of the channel region and element separation region, the result being non-uniformity in the characteristics of the memory cells.
For this reason, it is necessary to provide a sufficient diffusion layer width with respect to this variation, the result being the problem that the size of the memory cell increases.
In the Japanese Unexamined Patent Publication (KOKAI)No. 7-142618, there is disclosure of a method of forming a source region, and drain region, and an element separation region that are each self-aligning.
However, this method involves complex film growing processes, the number of process steps being large, and the cost being high, in addition to the problem that it is difficult to make the size of each individual transistor small.
Accordingly, it is an object of the present invention to improve on the above-noted drawbacks of the prior, by providing a semiconductor device in which the channel region, diffusion layer region, and element separation region of a transistor element are all established by one lithography step, the widths of each of these regions being thereby uniquely established, thereby enabling the suppression of non-uniformity in the characteristics of the memory cells and enabling the size of the transistor elements to be made small.
A further object of the present invention is to provide a method for manufacturing the above-noted semiconductor device.
SUMMARY OF THE INVENTION
In order to achieve the above-noted objects, the present invention adopts the following basic technical constitution.
Specifically, the first aspect of the present invention is a semiconductor device in which there is a plurality of transistor elements disposed on a substrate, these transistor elements being formed by a channel region, a source region, and a drain region, this semiconductor device being minimally provided with a first element separation region that is made of an insulating material and formed by a foot that protrudes from the substrate surface between the transistor elements of a pair of neighboring transistors toward the inside of the substrate and a wing that is connected to the above-noted foot, and that extends so as to cover the top of either the drain region or the source region of each of the neighboring transistor elements.
The second aspect of the present invention is a method for manufacturing a semiconductor device, this method having a first step of obtaining a multilayer film structure which is formed by the sequential forming, on a semiconductor substrate, of a silicon oxide film layer, a polysilicon film layer, a silicon oxide film layer, and a silicon nitride film layer, in that sequence, a second step of applying a resist mask to the above-noted silicon nitride film layer, and then using this resist mask to perform etching processing, thereby performing patterning of at least the silicon nitride film layer, the silicon oxide film layer, and the polysilicon film layer of the above-noted multilayer film structure, so that the multilayer film structure is minimally left in a region that is to be used for the formation, on the substrate, of a channel region and an element separation region, the multilayer film structure being removed in other regions of the substrate, a third step of removing the above-noted resist and the silicon oxide film on the substrate, a fourth step of forming a silicon film layer on the substrate surface and the side surface of the polysilicon film layer, a fifth step of implanting an impurity into the substrate via the silicon oxide film that was formed in the fourth step, so as to form a source diffusion layer and a drain diffusion layer, a sixth step of using a silicon oxide film filling the space that is formed between the opposing source region and drain region, a seventh step of covering the above-noted silicon oxide film with a resist film, and then performing etching while patterning this resist, so as to remove the silicon oxide film that opposes the part of the multilayer film structure in which an element separation part will be formed, an eighth step of removing the above-noted resist, and then further etching the above-noted silicon oxide film to remove the silicon nitride film layer, the silicon oxide film, and the polysilicon film layer that makes up the multilayer film structure in part of the substrate in which the element separation part is to be formed, this further etching thereby forming a trench in the substrate part in which the element separation part is to be formed, a ninth step of filling the entire above-noted trench with a silicon oxide film, and then either polishing or etching this silicon oxide film so as to expose the silicon nitride film layer of the multilayer film structure in a region of the substrate surface in which the channel region is to be formed, a tenth step of etching the above-noted silicon oxide film and etching the silicon nitride film layer and the silicon oxide film in the region of the multilayer film structure in which the channel region is to be formed, so as to expose the polysilicon film layer, and eleventh step of forming a polysilicon film layer on the above-noted polysilicon film layer and silicon oxide film layer, and performing prescribed patterning thereof, so as to leave part of the polysilicon film layer on the surface of the silicon oxide film, a twelfth step of forming an ONO film (silicon oxide film silicon nitride silicon oxide film structure) on the polysilicon film layer, and a thirteenth step of forming a polysilicon film on the above-noted ONO film.
By adopting the above-described technical constitution, a method for manufacturing a semiconductor device according to the present invention e
Bowers Charles
Kebede Brook
NEC Corporation
Sughrue Mion Zinn Macpeak & Seas, PLLC
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