Method of fabricating static random access memory with spacers

Details Method of fabricating static random access memory with spacers Method of fabricating static random access memory with spacers

2001-02-13

2001-12-04

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S210000, C438S595000

Reexamination Certificate

active

06326257

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a method of fabricating a memory device. More particularly, the invention relates to a method of fabricating a random access memory (SRAM).
2. Description of the Related Art
A static random access memory is a kind of semiconductor memory with a very high processing speed. In the typical design, a static random access memory comprises four transistors and two resistors (4T2R) or six transistors (6T). According to the demands of low power/low voltage, the static random access memory with six transistors is more stable.
According to the different functions, the static random access memory comprises different memory cells such as pull down device (PD), P type load device (PMOS load device, PL) and pass gate device (PG). The circuit structure is shown as FIG.
1
. As the dimension of the device shrinks, the stability becomes more important while the operation voltage of the memory cell in the static random access memory is dropped lower than 1.8 V.
Generally speaking, when the cell ratio of current between the pull down device and pass gate device is larger, the stability of the memory cell is higher. The typical memory cell fabrication method enhances the stability by increasing the current of the pull down device. However, to increase the operation speed of devices, the current of the pass gate device has to be increased. Consequently, the cell ratio is decreased, and the stability of the devices is lowered. Therefore, there is a tradeoff between the enhancement of the stability and the operation speed.
The method of fabricating a conventional static random access memory is shown as
FIGS. 2
,
3
and
4
.
FIG. 3
is a cross sectional view cutting along the line III—III of
FIG. 2
, while
FIG. 4
is a cross sectional view cutting along the line IV—IV. The conventional method includes forming the stacked gate of a pull down device, a PMOS load device, and a gate pass device
204
, a lightly doped drain/source region
206
, and a spacer
208
on each sidewall of the stacked gate
204
after an active region
202
is defined. A heavily doped ion implantation is performed, followed by a self-align silicide process to form a heavily doped drain/source region and metal silicide layers
210
and
212
thereon. A contact window
214
is then formed, and the following metallization process is performed.
As the spacer
208
has a significant thickness, the lightly doped source region
206
between the stacked gates of two neighboring memory cells
204
a
and
204
b
is covered with the spacer
208
as shown in FIG.
3
. Only a predetermined contact window region
216
of the lightly doped source region
206
is exposed, as shown in FIG.
4
. Thus, in the subsequent processes of heavily doped ion implantation and self-align silicidation, the heavily doped source region and the metal silicide layer are formed only on the contact region
216
. No heavily doped source region and metal silicide layer will be formed on the non-contact region
218
.
When the current flows from the drain region of the pull down device through the source region of the non-contact region
218
, being blocked by the spacer
208
, the source region comprises only the lightly doped source region. Therefore, a very high resistance is incurred.
In addition, while forming a contact window
214
to connect a ground voltage Vss on the lightly doped source region
206
, once misalignment occurs, the contact window
214
shifts towards the non-contact region
218
, to partly be on the spacer
208
on the non-contact region
218
. As a result, the contact area between the contact window
214
and the contact region
216
is decreased, so that the resistance of the source region is greatly increased.
The above conventional method for fabricating the static random access memory increases the resistance of the source region. Consequently, the current of the pull down device is reduced to reduce the cell ratio. The stability of the static random access memory is thus greatly affected.
SUMMARY OF THE INVENTION
The invention provides a method of fabrication a static random access memory with a reduced resistance of the source region.
The method provided by the invention further has the advantage of maintaining the cell ratio between the pull down device and the pass gate device while operating the low power/low voltage static random access memory.
In one embodiment of the invention, the method of fabricating a static random access memory comprises the following steps. A stacked gate is formed on a substrate. A lightly doped source region and a lightly doped drain region are formed in the substrate. A thin spacer is formed on one sidewall of the stacked gate. The thin spacer covers only a part of the lightly doped source region, such that the other part of the lightly doped source region is exposed. A thick spacer is formed on the other sidewall of the stacked gate on the lightly doped drain region only. Using the thin and thick spacers as a mask, an ion implantation step is performed to form a heavily doped source region and a heavily doped drain region. A self-aligned silicidation step is performed to form a metal silicide layer on the stacked gate, a source region including the lightly and the heavily doped source regions, and a drain region including the lightly and the heavily doped drain region.
In the above embodiment, a cap layer is formed on a gate conductive layer of the stacked gate before performing a photolithography and etching step on the stacked gate. A stacked gate with a cap layer is then defined using the photolithography and etching step. A thin spacer is then formed on each sidewall of the stacked gate. A patterned photoresist layer is formed to cover a side of the substrate and one of the thin spacers. Using the patterned photoresist layer as a mask, one of the thin spacers is removed to leave the thin spacer on only one of the sidewalls of the stacked gate. The photoresist layer and the cap layer are removed. An insulating layer is formed over the substrate. The insulating layer is then etched back using anisotropic etching to form a thick spacer on the exposed sidewall of the stacked gate. Meanwhile, a residue of the insulating layer is remained around the thin spacer. The residue of the insulating layer is then removed to leave the thin spacer on one sidewall, and the thick spacer on the other sidewall of the stacked gate. Using the thin and thick spacers as a mask, an ion implantation is performed to form a source region including a heavily and a lightly doped source region and a drain region including a heavily and a lightly doped drain region in the substrate. Using a self-aligned silicidation, a metal silicide layer is formed on the stacked gate, the source region and the drain region.
As the thin spacer has a thickness far smaller than the conventional spacer, a metal silicide layer with a larger area can thus be formed on the source region to reduce the resistance thereof. As a result, the cell ratio between the pull down device and the pass gate device under the low voltage operation condition can thus be increased. The stability can thus be enhanced.
In the invention, only the gate oxide layer at the side of the drain region has a bird's beak shape. The gate oxide layer at other places is thin and uniform. Therefore, not only the drain leakage current incurred by the gate can be reduced, but also the resistance of the source region can be reduced. As a result, the cell ratio between the pull down device and the pass gate device of the low power/low voltage is maintained during operation. The stability of the static random access memory is increased.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 5264385 (1993-11-01), Roberts
patent: 5416034 (1995-05-01), Bryant
patent: 5770496 (1998-06-01), Roberts

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