Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-09-21
2001-10-16
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S432000, C438S592000
Reexamination Certificate
active
06303443
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89116895, filed Aug. 21, 2000.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a method of fabricating an electrostatic discharge (ESD) protection device. More particularly, this invention relates to a method of fabricating a self-aligned silicide (salicide) layer in an electrostatic discharge protection device.
2. Description of the Related Art
In a conventional electrostatic discharge protection device, if a salicide layer is formed on the drain region thereof, the electrostatic current is easily localized to cause the junction to be locally burned and damaged. Once the junction is damaged, the protection function can never be achieved. To solve such problem, a method using salicide layer is provided and shown in
FIG. 1A
to FIG.
1
C.
In
FIG. 1A
, on a substrate
100
having a shallow trench isolation
102
, a gate
104
, a source region
106
a
and a drain region
106
b
are formed. A salicide block layer
108
is formed to cover the gate
104
, the source region
106
a
and the drain region
106
b
. A mask layer
110
is formed to cover the salicide block layer
108
on the drain region
106
b
. To ensure the salicide block layer
108
covering the drain region
106
b
is completely covered, it is often that the salicide block layer
108
is formed to cover a portion of the gate
104
next to the drain region
106
b
. Typically, according to the design rule, the width of the gate to be covered with the mask layer
110
is about 0.3 micron.
In
FIG. 1B
, the exposed salicide block
108
layer is removed to expose the source region
106
a
and a portion of the gate
104
, while the drain region
106
b
is still covered with the remaining salicide block layer
108
a.
In
FIG. 1C
, a salicide layer
112
is formed on the exposed source region
106
a
and a portion of the gate
104
. As shown in
FIG. 1C
, the drain region
106
b
is free from formation of the salicide layer
112
for being covered with the salicide block layer
108
a.
Therefore, when the device approaches a second breakdown, the ballast resistance of the drain region
106
b
prevents current localization, and thus, prevents the junction from being damaged thereby. However, as a portion of the gate
104
is also covered with the salicide block layer
108
while forming the salicide layer
112
, the resistance of the gate
104
is thus remained at a certain high magnitude. As the integration of the integrated circuit increases, the line width of the gate consequently shrinks, the high resistance of the gate more and more seriously affects the electrical performance of the device.
In a typical conventional electrostatic discharge protection integrated circuit (IC), I/O driving transistors are connected with electrostatic discharge protection transistors in parallel. When electrostatic discharge occurs, the I/O driving transistors are switched to function as the electrostatic discharge protection transistors to share the electrostatic discharge current. Therefore, for these I/O driving transistors, in addition to protecting the junction from being damaged, it is also important to maintain the IC speed, such that the performance of the devices does not deteriorate. With the conventional method, since the salicide layer can only be formed on a portion of the gate, this requirement can hardly be met.
SUMMARY OF THE INVENTION
The invention provides a method of fabricating a salicide layer in an electrostatic discharge protection device. A MOS transistor comprising at least a gate, a drain region and a source region is provided. The gate is covered with an anti-reflection coating layer. A salicide block layer is formed to cover the source region and the drain region. The salicide block is patterned to expose the source region, while the drain region is still covered by the salicide block layer. The anti-reflection coating layer is removed to expose the gate after the salicide block layer is patterned. A salicide layer is then formed on the source region and the gate, while the drain region is free of formation of the salicide layer for being covered with the remaining salicide block layer.
In the method mentioned above, the drain region is covered with the salicide block layer while forming the salicide layer. Therefore, there is no salicide layer formed on the drain region. Current localization does not occur to damage the junction. In addition, with the anti-reflection coating layer, the salicide block layer is not formed on the gate. After the salicide block layer is patterned, the anti-reflection coating layer is removed to expose the whole gate. The gate surface is completely covered with the salicide layer. The resistance of the gate can thus be effectively reduced to ensure the required IC speed.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
REFERENCES:
patent: 4877755 (1989-10-01), Rodder
patent: 5413969 (1995-05-01), Huang
patent: 5891784 (1999-04-01), Cheung
patent: 5933739 (1999-08-01), Lin
patent: 5946573 (1999-08-01), Hsu
patent: 6121092 (2000-09-01), Liu
patent: 6130146 (2000-10-01), Chang et al.
Booth Richard
Thomas Kayden Horstemeyer & Risley LLP
United Microelectronics Corp.
Whitmore Stacy
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