Method of forming a capacitor for a semiconductor memory device

Details Method of forming a capacitor for a semiconductor memory device Method of forming a capacitor for a semiconductor memory device

2000-06-30

2001-11-13

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S240000, C438S241000, C438S242000, C438S243000, C438S785000, C438S786000, C438S778000

Reexamination Certificate

active

06316307

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method of forming a capacitor for a semiconductor memory device, and more particularly to a method forming a capacitor for a semiconductor memory device using a TaON layer as a dielectric.
BACKGROUND OF THE INVENTION
Along with the recent progress in the semiconductor manufacturing technology, the demand for memory device has increased dramatically. Consequently, a memory device having high capacitance in comparison with narrow area is required. Capacitance of the capacitor is increased by using an insulator having high dielectric constant or enlarging the surface area of a lower electrode. Those conventional capacitors have used a tantalum-oxide(Ta
2
O
5
) layer having a dielectric constant higher than that of a nitride-oxide (NO) layer as a dielectric, thereby forming the lower electrode having 3-Dimensional structure.
FIG. 1
is a cross-sectional view showing a capacitor for a conventional semiconductor memory device. Referring to
FIG. 1
, a gate electrode
13
including a gate insulating layer
12
at a lower portion thereof is formed by a known technology on the upper part of a semiconductor substrate
10
which a field oxide layer is formed at a selected portion thereof. A junction region
14
is formed on the semiconductor substrate
10
at both sides of the gate electrode
13
, thereby forming an MOS transistor. A first interlevel insulating layer
16
and a second interlevel insulating layer
18
are formed on the upper part of the semiconductor substrate
10
which the MOS transistor is formed thereon. A storage-node contact hole h is formed in the first and the second interlevel insulating layers
16
and
18
so that the junction region
14
is exposed. A cylinder type lower electrode
20
is formed by a known technology in the storage-node contact hole h to be contacted with the exposed junction region
14
. A hemi-Spherical grain(HSG) layer
21
is formed on the surface of the lower electrode
20
in order to increase the surface area of the lower substrate
20
. A Ta
2
O
5
layer
23
is formed on the surface of the HSG layer
21
. At this time, the Ta
2
O
5
layer
23
is formed as follows. First, a surface of the HSG layer
21
is cleaned before the Ta
2
O
5
layer
23
is formed, and then the RTN(rapid thermal nitration) process is performed ex situ, thereby forming a silicon-nitride layer
22
on the surface of the HSG layer
21
. Next, a first Ta
2
O
5
layer is formed at temperature of approximately 400~450° C. to the thickness of 53~57 Å. Afterward, an annealing process is performed at low temperature, and a second Ta
2
O
5
layer is formed to the same thickness and by the same process as in the first Ta
2
O
5
layer. Annealing processes at low temperature and at high temperature are continued in series, thereby forming a single Ta
2
O
5
layer
23
. An upper electrode
24
is deposited on upper parts of the Ta
2
O
5
layer
23
and the second interlevel insulating layer
18
, thereby completing the formation of a capacitor.
However, the conventional capacitor formed according to the above method using the Ta
2
O
5
as a dielectric has the following problems.
First, a difference in the composition rate of Ta and O is generated since a general Ta
2
O
5
layer has unstable stoichiometry. As a result, substitutional Ta atoms, i.e. vacancy atoms, are generated in a thin film. Since those vacancy atoms are oxygen vacancies, leakage current is generated. The amount of vacancy atoms can be controlled depending on the contents and the bonding strength of components in the Ta
2
O
5
layer; however, it is difficult to eliminate them completely.
The Ta
2
O
5
layer is oxidized so as to remove the substitutional Ta atoms therein in order to stabilize the unstable stoichiometry thereof. However, when the when the Ta
2
O
5
layer is oxidized to prevent leakage current, the following problems are generated. That is, the Ta
2
O
5
layer has high oxide reaction with the upper and the lower electrodes formed of polysilicon or TiN and so forth. Therefore, in a process oxidizing the substitutional Ta atoms, an oxide layer having low dielectric constant is formed at an interface since the Ta
2
O
5
layer and the upper electrode or the lower electrode react to one another, and oxygen moves to the interface between the Ta
2
O
5
layer and the lower electrode, thereby deteriorating the homogeneity thereof.
Further, due to the reaction between an organic substance such as Ta(OC
2
H
5
)
5
used as a precursor and O
2
(or N
2
O) gas, impurities such as carbon atoms C, carbon compounds (CH
4
, C
2
H
4
) and H
2
0
are generated in the Ta
2
O
5
layer. These impurities increase leakage current in the capacitor and deteriorate the dielectric characteristics of the Ta
2
O
5
layer. Accordingly, a capacitor having a large capacitance is difficult to obtain.
Moreover, in a method of using a tantalum oxide layer as a dielectric layer, before the formation of the tantalum oxide layer and after the cleaning process, extra ex-situ process is performed, the tantalum oxide layer is deposited in two steps, and two times of thermal processes are performed at low and high temperatures after the formation of the tantalum oxide layer. Therefore, a manufacturing process is cumbersome.
SUMMARY OF THE INVENTION
Accordingly, it is one object of the present invention to provide a method of forming a capacitor for a semiconductor device capable of ensuring a great capacitance by providing a dielectric layer having low leakage current and high dielectric constant.
To achieve the object of the present invention, the present invention provides a method of forming a capacitor for a semiconductor memory device comprising the steps of: forming a lower electrode on a semiconductor substrate; performing a surface-treatment process to prevent a natural oxide layer from generating on the surface of the lower electrode; forming a TaON layer on the upper part of the surface-treated lower electrode by a reaction of Ta chemical vapor, O
2
gas and NH
3
gas; crystallizing the TaON layer; and forming an upper electrode on the upper part of the TaON layer, wherein the TaON layer is formed in a low pressure chemical vapor deposition(LPCVD) chamber equipped with a shower head injecting Ta chemical vapor, O
2
gas and NH
3
gas on an upper part thereof and at a temperature of 300 to 600° C. with pressure of 0.1 to 10 Torr.
Moreover, according to another embodiment of the present invention, the present invention provides a method of forming a capacitor for a semiconductor memory device comprising the steps of: forming a lower electrode on the semiconductor substrate; performing a surface-treatment process to prevent a natural oxide layer from generating on the surface of the lower electrode; forming a TaON layer on the upper part of the surface-treated lower electrode by a reaction of Ta chemical vapor, O
2
gas and NH
3
gas; crystallizing the TaON layer; and forming an upper electrode on the upper part of the TaON layer, wherein the TaON layer is formed in an LPCVD chamber that a first injector to which Ta chemical vapor and O
2
gas are injected and formed at one side-wall of the chamber and a second injector to which NH
3
gas is injected and formed at the other side-wall opposed to the first injector, thereby injecting reaction gases in a counter-flow state, and the TaON layer is formed at a temperature of 300 to 600° C. with pressure of 0.1 to 10 Torr.
Further, the present invention further provides a method of manufacturing a capacitor for a semiconductor memory device comprising steps of: forming a lower electrode on the semiconductor substrate; performing a surface-treatment process to prevent a natural oxide layer from generating on the surface of the lower electrode; forming a TaON layer on the upper part of the surface-treated lower electrode by a reaction of Ta chemical vapor, O
2
gas and NH
3
gas; crystallizing the TaON layer; and forming an upper electrode on the upper part of the TaON layer, wherein the TaON layer is formed in an LPCVD chamb

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