Method of forming the capacitor in DRAM

Details Method of forming the capacitor in DRAM Method of forming the capacitor in DRAM

2000-07-20

2001-10-30

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S255000, C438S243000, C438S398000

Reexamination Certificate

active

06309923

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to a method for forming a capacitor in DRAM, particularly relates to a method of forming a capacitor utilizing the self-align contact structure.
BACKGROUND OF THE INVENTION
As the semiconductor memory device becomes more highly integrated, to decrease the contact area is a possibility to contribute to the high integrated circuits. SAC (Self-Align Contact) method is one example. To shrink the area occupied by a capacitor of a DRAM storage cell is another possibility, however it will cause the capacitance reduce of the capacitor. Owing to the leakage current, it is necessary to refresh the capacitor continuously in order to keep the stored state, especially when the capacitance of the capacitor is limited. Furthermore, the area reduction of the capacitor occupied will cause the capacitor to be disturbed by the alpha particle more easily.
Until now, there has been much effort directed to keep a relatively large capacitance of the capacitors in order to achieve a high signal to noise ratio in reading the memory cell and to reduce soft errors (due to alpha particle interference) as the memory device becomes highly integrated. As the followings, there are some approaches to increase the storage capability of the capacitor while the area occupied by the capacitor maintains small enough. (1) substituting a high capacitance material for traditional material to increase the storage charges per unit area of the capacitor, for example: the substitution the of Ta
2
O
5
and TiO
2
for SiO
2
. (2) decreasing the dielectric layer thickness of the capacitor: because of the Fowler-Nordheimn tunneling effect, the dielectric layer thickness is limited to a minimum value and one can not improve the capacitor too much by this method. (3) variation the shape of the capacitor electrodes: the capacitor may have protrusions, cavities, etc., to increase the surface area of the capacitor electrode. (4) increasing the contact area between the conductive layer acting as the electrode of the capacitor and the dielectric layer: the surface between the dielectric layer and the conductive layer can be varied to a ragged type surface and not be even a plain surface anymore.
One type of increasing the contact area is a ragged polysilicon layer or hemispherical grain (HSG) polysilicon. The present invention concerns the issue of increasing the capacitance in self-align contact (SAC) structure, which utilize the aforementioned third and fourth approach.
SUMMARY OF THE INVENTION
The present invention provides a method for manufacturing capacitor in DRAM utilizing self-align contact structure.
In the present invention, two word line structures, active areas are provided on the substrate. First, a first dielectric layer is deposited on the active region and the word line with planar top surface. Next, a contact hole is created in the first dielectric layer to expose portions of said active region and said word line by using plasma etch process in consequence. Furthermore, a conductive layer is formed on the substrate and is etched back until the thickness within the range about 100 to 5000 angstroms.
Then, a polysilicon spacer with the width range about 50 to 2000 angstroms is formed on the sidewall of the contact hole, and a dielectric spacer with the width range about 100 to 2000 angstroms is formed on the sidewall of said polysilicon spacer. Afterward, the maining space of the contact hole is filled with a polysilicon bar and three sub-contact holes are created by etching back the polysilicon spacer and the polysilicon bar with part of the polysilicon spacer and said polysilicon bar remaining on the bottom. The polysilicon spacer and the polysilicon bar have the thickness range about 50 to 1000 angstroms. Next, a hemispherical grain (HSG) layer is formed on the surface of said sub-contact holes, and a second dielectric layer is dopesited on the hemispherical grain. Finally, a top electrode is formed on the second dielectric layer to complete the capacitor fabrication.


REFERENCES:
patent: Re. 36786 (2000-07-01), Fazan et al.
patent: 5447878 (1995-09-01), Park et al.
patent: 6027981 (2000-02-01), Wu
patent: 6218242 (2001-04-01), Tseng
patent: 6222722 (2001-04-01), Fukuzumi et al.

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