Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2000-04-03
2001-10-16
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S149000, C438S412000, C438S479000, C438S517000, C257S347000, C257S350000, C257S353000, C257S355000
Reexamination Certificate
active
06303412
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor devices and fabrication methods, and more particularly to methods of fabricating semiconductor-on-insulator devices and devices formed thereby.
BACKGROUND OF THE INVENTION
Electronic devices may be formed on thin-film silicon-on-insulator (SOI) substrates with reduced short channel effects, reduced parasitic and nodal capacitances, increased radiation hardness, reduced susceptibility to parasitic thyristor latch-up and reduced process complexity compared to bulk semiconductor devices. However, SOI devices may have parasitic contact resistances, such as high source and drain contact resistances to SOI MOSFETs.
One attempt to form an SOI MOSFET according to the prior art is disclosed in
FIGS. 1A-1D
. In particular, to form the structure of
FIG. 1A
, a buried oxide layer
12
and a silicon layer
14
thereon are formed using a conventional separation by implantation of oxygen (SIMOX) technique which involves implanting oxygen ions into a face of a silicon substrate
10
. Then, a pad oxide layer
16
, nitride layer
18
and photosensitive patterning layer
20
are sequentially formed. The nitride layer
18
is then patterned to define an active region in the silicon layer
14
using the photosensitive layer
20
as a mask. Field oxide isolation regions
22
are then formed by performing a relatively long and high temperature oxidation of the silicon layer
14
until the silicon layer
14
is consumed, using the patterned nitride layer
18
as a mask, as illustrated by FIG.
1
B. The nitride layer
18
is then removed and impurity ions are-implanted into the silicon layer
14
to set the threshold voltage. An insulated gate electrode comprising a gate insulating layer
26
, polycrystalline silicon and tungsten silicide (WSi
x
) gate electrode
28
and oxide spacers
30
, is then formed on the silicon layer
14
. The gate electrode
28
is then used as a mask to form the source region
14
a
and drain region
14
b
in the silicon layer
14
, as illustrated by FIG.
1
C. Conventional steps are then used to deposit an insulating layer
32
and then reflowing boro-silicate glass (BPSG) on the insulating layer
32
to form a planarized layer
34
. The planarized layer
34
and insulating layer
32
are then etched to form source and drain contact holes. Source and drain electrodes
36
and
38
are then formed by patterning metallization on the planarized layer
34
, as illustrated by FIG.
1
D.
Unfortunately, the use of thin-film SOI substrates typically causes an increase in the sheet resistances of the source and drain regions of FETs formed therein and this increase typically causes a decrease in on-state current (I
ds
). These difficulties in using thin-films are more fully disclosed in an article by L. Su et al. entitled
Optimization of Series Resistance in Sub
-0.2
&mgr;m SOI MOSFETs
, International Electron Devices Meeting, No. 30.1.1-30.1.4, pp. 723-726. However, the use of thick-film SOI substrates is also problematic because high junction capacitances with the channel region typically result and because sub-threshold leakage current typically increases with the thickness of the silicon film.
Thus, notwithstanding prior art attempts to form SOI substrates and devices, there still continues to be a need for improved methods of forming SOI substrates and devices so that devices formed therein derive the above described benefits of SOI isolation, but do not suffer from high sheet resistances and high junction capacitances associated with thin-film devices.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved methods of forming semiconductor-on-insulator substrates and devices, and structures formed thereby.
It is another object of the present invention to provide methods of forming semiconductor-on-insulator substrates and devices having low source and drain sheet resistances and low source and drain contact resistances, and structures formed thereby.
It is still a further object of the present invention to provide methods of forming semiconductor-on-insulator substrates and devices having low junction capacitance between the source and drain regions and the channel region therebetween, and structures formed thereby.
These and other objects, features and advantages of the present invention are provided by methods of forming semiconductor-on-insulator field effect transistors which include the steps of forming an insulated trench containing a semiconductor region therein and an insulating region mesa at a bottom of the trench, so that the semiconductor region has relatively thick regions adjacent the sidewalls of the trench and has a relatively thin region above the mesa. Dopants can then be added to the thick regions to form low resistance source and drain regions on opposite sides of the thin region which acts as the channel region. Because the channel region is thin, low junction capacitance can also be achieved. An insulated gate electrode can also be formed on the face of the semiconductor region, above the channel region, and then source and drain contacts can be formed to the source and drain regions to complete the device.
Preferably, the step of forming the trench containing a semiconductor region comprises the steps of patterning an oxidation blocking layer having an opening therein, on a face of a semiconductor substrate, and then oxidizing the substrate at the face to form an electrically insulating region in the opening and adjacent the oxidation blocking layer. These steps are performed so that a portion of the electrically insulating region in the opening is thinner than a portion of the electrically insulating region extending adjacent the edges of the oxidation blocking layer. Next, the oxidation blocking layer is removed from the face of the substrate and then the electrically insulating region is planarized. The planarized insulating region is then used as a substrate by planarizing a back face of the semiconductor substrate until the insulating region is reached. At this point an insulated trench filled with a semiconductor material will remain in the insulating region. This remaining semiconductor material can then be used as an SOI substrate.
REFERENCES:
patent: 5011783 (1991-04-01), Ogawa et al.
patent: 5436173 (1995-07-01), Houston
patent: 5496764 (1996-03-01), Sun
patent: 5510640 (1996-04-01), Shindo
patent: 5893745 (1999-04-01), Park
patent: 6064092 (1999-04-01), Park
Lee Granvill D
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
Smith Matthew
LandOfFree
Methods of forming semiconductor-on-insulator substrates and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods of forming semiconductor-on-insulator substrates and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of forming semiconductor-on-insulator substrates and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2573156