Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-06-12
2001-02-06
Butler, Dennis M. (Department: 2787)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C716S030000, C716S030000
Reexamination Certificate
active
06185706
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to performance testing of semiconductor devices, and more particularly to process monitor structures for accurately predicting the across-the-die performance of an integrated circuit die.
2. Description of the Related Art
Improvements in semiconductor processes are making possible integrated circuits of increasing size and complexity. The semiconductor processing technologies that produce these integrated circuits have advanced to the point where complete systems can now be reduced to a single integrated circuit or application specific integrated circuit (ASIC) device. These integrated circuits (also referred to as “die” or “chips”) may use many functions that previously could not be implemented on a single die. It is a common practice for the manufacturers of such integrated circuits to thoroughly test device functionality at the manufacturing site. However, due to the complex nature of today's integrated circuits and a concomitant sensitivity to variations in manufacturing processes, manufacturers are constantly confronted with new testing challenges.
In addition, interconnecting the millions of transistors that may be present on a chip also poses difficulties. To aid in this task, new multiple layer metallization schemes have been developed that allow up to five or more distinct “levels” or layers of metal interconnect wires. In such multiple layer metallization schemes, the various metal interconnect wires typically have different nominal widths and heights, different distances from transistor gates, and are insulated by oxide layers of varying thickness. These differences in the physical properties of the metal layers cause different metal layers to exhibit somewhat dissimilar electrical characteristics, resulting in disparities in propagation delays that a signal experiences when communicated over routing wires formed from the different metal layers.
Often, the performance of the integrated circuitry can be dominated by propagation delays through longer metal interconnect wires rather than the basic gate delays of individual logic elements. This phenomenon is exacerbated by the fact that as the width of a wire shrinks in deep submicron designs, the resistance of the wire may increase more rapidly than capacitance decreases. An increase in average propagation delays frequently results in a greater number of critical timing paths (e.g., signal paths in which best or worst case simulated propagation delays may approach the limits required for proper functionality). Many circuit timing problems involve such critical timing paths.
In order to avoid timing and other problems, integrated circuits are typically simulated in a software environment, using a variety of CAE tools, before the integrated circuits are actually fabricated. Such simulations function to reduce costly physical design iterations because modifications to an integrated circuit design are more readily achieved in software. Given the complexity of today's integrated circuits, accurate simulation is thus essential to a successful integrated circuit design.
Following fabrication of an integrated circuit, testing is performed to insure that the integrated circuit functions as designed. Although the integrated circuit may work functionally, it may not operate at the clock frequency at which it was designed to operate. Certain testing methodologies are employed to verify that the integrated circuit works “at speed.” One such method is to test all circuitry functionally at the highest frequency at which the integrated circuit is designed to operate. At speed testing is typically not performed, however, because it is extremely difficult to create test patterns to check integrated circuits at high frequencies. Further, specialized testers are also required.
As a result, another method used to verify at speed functionality involves measuring predetermined critical paths and assume that if these critical paths meet the timing specifications, all other paths are within specification. However, identification and measurement of critical paths is sometimes difficult.
To address these difficulties, process monitoring circuitry has been developed that resides on the integrated circuit itself. One such process monitor is the “PROCMON” cell developed by LSI Logic Corporation of Milpitas, Calif. The PROCMON circuits are analyzed during testing and their performance serves as a parametric indication of the integrity of the manufacturing process.
In complementary metal-oxide-semiconductor (CMOS) circuits, the performance of the integrated circuit depends on the performance of both p-channel (PMOS) and n-channel (NMOS) transistors. Since the PMOS and NMOS transistors are formed at different stages of the manufacturing process, process variations at a given step may not affect the PMOS and NMOS transistors equally. The PROCMON cell includes a short and long delay paths providing a first edge delay pulse in response to a logic level high to a logic low transition signal at the input terminal, and providing a second edge delay pulse when a logic low to logic high transition signal is provided at the same input terminal. The differences between the edge delay pulses are indicative of the relative performance of the PMOS and NMOS transistors being monitored.
However, given the increased length of routing that is frequently encountered in today's integrated circuits, the PROCMON cell may not take into account delays associated with long metal lines and/or a multitude of vias in certain delay paths. The PROCMON cell does monitor “short” and “long” signal paths, however the “long” signal path is typically contained within the cell itself and may not reflect actual routing. Because the long metal paths are contained within the PROCMON cell, length of routing and the number of vias that can be utilized are also limited. In addition, process monitor circuits such as the PROCMON cell are typically routed in the first layer of interconnect metal. Therefore, if a process problem develops that effects the resistance or capacitances of different metal layers or vias, the current process monitors may not detect such problems.
Further, the relatively compact size and localized placement of current process monitor structures do not allow these structures to provide information reflecting across-the-die manufacturing process variations. With the current circuitry, the assumption is made that the process is uniform across the die. The performance of transistors is, to the first order, mainly determined by the critical dimension of transistor polysilicon gate lengths. Unfortunately, the uniformity of the critical dimension of the polysilicon gate lengths is not always within acceptable limits across a die due to a variety of possible process and equipment variations.
SUMMARY OF THE INVENTION
Briefly, performance monitoring circuitry according to the present invention includes test structures placed across the integrated circuit die to monitor performance of the silicon across the die. Process variations that effect the performance of transistors and routing can thus be detected, even if such variations are localized in nature.
More specifically, by monitoring the performance of standard inverters (or other logic gates configured as inverter circuits) dispersed across an integrated circuit, the integrity of the semiconductor process used to manufacture a particular integrated circuit can ascertained through comparison to simulations values for the logic gates. This information can be used to determine whether any process induced problems could effect the performance of the integrated circuit in its final application. If mismatches between silicon and simulations are discovered, the invention allows for a determination as to whether the mismatches are attributable to N-channel transistors, P-channel transistors or other process issues.
In one embodiment in the invention, inverters are arranged in such a fashion that across-the-die performance checks can be p
Butler Dennis M.
LSI Logic Corporation
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